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riscv: semihosting: correct alignment

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Commit 7400d34ba9 ("riscv: semihosting: replace inline assembly with
assembly file") reduced the alignment of function smh_trap().

As described in the "RISC-V Semihosting" specification [1] the ssli,
ebreak, and srai statements must all reside in the same memory page.

[1] RISC-V Semihosting, Version 0.4, 12th June 2024
    https://github.com/riscv-non-isa/riscv-semihosting

Fixes: 7400d34ba9 ("riscv: semihosting: replace inline assembly with assembly file")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This commit is contained in:
Heinrich Schuchardt
2024-06-19 17:22:52 +02:00
committed by Leo Yu-Chi Liang
parent 66b5ee9c55
commit 36756308a2
1 changed files with 1 additions and 1 deletions
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2
arch/riscv/lib/semihosting.S
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@@ -8,7 +8,7 @@
.pushsection .text.smh_trap, "ax"
ENTRY(smh_trap)
.align 2
.align 4 /* keep slli, ebreak, srai in same page */
.option push
.option norvc /* semihosting sequence must be 32-bit wide */