rockchip: Add a generic-ddr3 rk3399 board
This build-target is used to build an image which can run on multiple rk3399 boards, using VBE to boot. To use it, the TPL binary for a particular board must be placed into the first part of the image. The rest of the image (i.e. VPL, SPL and U-Boot) are largely generic and can work on any supported board. With VBE, memory-init happens in SPL so that this code is updatable in the field. Due to size constraints, the type of memory on the board is defined at build-time. So it is not possible to use the same VBE image on boards with different SDRAM (DDR3 vs LPDDR4 for example). This may become possible with newer boards with more SRAM. Series-changes: 2 - Rename to rk3399-generic-ddr3 - Update devicetree to match firefly-rk3399 - Use the firefly devicetree as the default for this board Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass
@@ -89,3 +89,9 @@ M: Jagan Teki <jagan@amarulasolutions.com>
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S: Maintained
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F: configs/rock-pi-n10-rk3399pro_defconfig
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F: arch/arm/dts/rk3399pro-rock-pi-n10*
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RK3399-GENERIC-DDR3
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M: Simon Glass <sjg@chromium.org>
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S: Maintained
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F: configs/rk3399-generic-ddr3_defconfig
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F: arch/arm/dts/rockchip-vpl-u-boot.dtsi
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124
configs/rk3399-generic-ddr3_defconfig
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124
configs/rk3399-generic-ddr3_defconfig
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@@ -0,0 +1,124 @@
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CONFIG_ARM=y
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CONFIG_SKIP_LOWLEVEL_INIT=y
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CONFIG_SPL_SYS_DCACHE_OFF=y
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CONFIG_COUNTER_FREQUENCY=24000000
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_TEXT_BASE=0x00200000
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x3f00000
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CONFIG_SF_DEFAULT_SPEED=20000000
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CONFIG_ENV_OFFSET=0x3F8000
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CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-firefly"
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CONFIG_DM_RESET=y
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CONFIG_ROCKCHIP_RK3399=y
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CONFIG_TARGET_EVB_RK3399=y
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CONFIG_SPL_STACK=0xff8eff00
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CONFIG_SPL_TEXT_BASE=0xff8c2000
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CONFIG_SPL_BSS_MAX_SIZE=0x2000
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CONFIG_SPL_STACK_R=y
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CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x30000
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CONFIG_SYS_LOAD_ADDR=0x800800
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CONFIG_DEBUG_UART_BASE=0xFF1A0000
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CONFIG_DEBUG_UART_CLOCK=24000000
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CONFIG_PCI=y
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CONFIG_DEBUG_UART=y
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CONFIG_FIT_BEST_MATCH=y
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CONFIG_VPL_LOAD_FIT_FULL=y
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# CONFIG_VPL_FIT_PRINT is not set
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# CONFIG_VPL_FIT_SIGNATURE is not set
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# CONFIG_VPL_BOOTSTD is not set
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# CONFIG_BOOTMETH_VBE_SIMPLE is not set
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CONFIG_BOOTMETH_VBE_ABREC=y
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CONFIG_BOOTSTAGE=y
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CONFIG_BOOTSTAGE_REPORT=y
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CONFIG_USE_PREBOOT=y
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CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-generic.dtb"
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CONFIG_LOG=y
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CONFIG_DISPLAY_BOARDINFO_LATE=y
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CONFIG_BLOBLIST=y
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CONFIG_BLOBLIST_FIXED=y
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CONFIG_BLOBLIST_ADDR=0xff8eff00
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CONFIG_BLOBLIST_SIZE=0x100
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CONFIG_SPL_MAX_SIZE=0x40000
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CONFIG_SPL_PAD_TO=0x7f8000
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# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
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CONFIG_SPL_HAVE_INIT_STACK=y
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# CONFIG_SPL_SEPARATE_BSS is not set
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CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1000
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CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
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CONFIG_TPL=y
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CONFIG_TPL_RELOC_LOADER=y
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CONFIG_VPL=y
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CONFIG_VPL_RELOC_LOADER=y
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CONFIG_CMD_BOOTZ=y
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CONFIG_CMD_GPT=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_PCI=y
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CONFIG_CMD_USB=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_TIME=y
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CONFIG_CMD_BOOTSTAGE=y
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CONFIG_SPL_OF_CONTROL=y
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CONFIG_OF_LIST="rockchip/rk3399-nanopc-t4 rockchip/rk3399-nanopi-m4 rockchip/rk3399-nanopi-m4b rockchip/rk3399-nanopi-neo4 rockchip/rk3399-evb rockchip/rk3399-ficus rockchip/rk3399-firefly rockchip/rk3399-orangepi rockchip/rk3399-puma-haikou"
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CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
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CONFIG_ENV_IS_IN_MMC=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_TPL_DM_SEQ_ALIAS=y
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CONFIG_VPL_REGMAP=y
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CONFIG_VPL_SYSCON=y
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CONFIG_SPL_CLK=y
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CONFIG_ROCKCHIP_GPIO=y
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CONFIG_SYS_I2C_ROCKCHIP=y
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CONFIG_ROCKCHIP_IODOMAIN=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_SDMA=y
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CONFIG_MMC_SDHCI_ROCKCHIP=y
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CONFIG_PHY_REALTEK=y
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CONFIG_DM_ETH_PHY=y
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_GMAC_ROCKCHIP=y
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CONFIG_NVME_PCI=y
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CONFIG_PHY_ROCKCHIP_INNO_USB2=y
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CONFIG_PHY_ROCKCHIP_TYPEC=y
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# CONFIG_SPL_DM_PMIC is not set
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CONFIG_PMIC_RK8XX=y
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CONFIG_REGULATOR_PWM=y
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CONFIG_REGULATOR_RK8XX=y
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CONFIG_PWM_ROCKCHIP=y
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CONFIG_BAUDRATE=1500000
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CONFIG_DEBUG_UART_SHIFT=2
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CONFIG_SYS_NS16550_MEM32=y
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CONFIG_SYSRESET=y
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# CONFIG_VPL_SYSRESET is not set
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CONFIG_USB=y
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# CONFIG_SPL_DM_USB is not set
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_EHCI_GENERIC=y
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CONFIG_USB_DWC3=y
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CONFIG_USB_DWC3_GENERIC=y
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CONFIG_USB_HOST_ETHER=y
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CONFIG_USB_ETHER_ASIX=y
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CONFIG_USB_ETHER_ASIX88179=y
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CONFIG_USB_ETHER_MCS7830=y
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CONFIG_USB_ETHER_RTL8152=y
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CONFIG_USB_ETHER_SMSC95XX=y
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CONFIG_VIDEO=y
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CONFIG_DISPLAY=y
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CONFIG_VIDEO_ROCKCHIP=y
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CONFIG_DISPLAY_ROCKCHIP_HDMI=y
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CONFIG_VPL_USE_TINY_PRINTF=y
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CONFIG_SPL_TINY_MEMSET=y
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CONFIG_CMD_DHRYSTONE=y
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# CONFIG_SPL_SHA1 is not set
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# CONFIG_VPL_SHA1 is not set
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# CONFIG_VPL_SHA256 is not set
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CONFIG_TPL_CRC8=y
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CONFIG_TPL_LZ4=y
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CONFIG_VPL_LZ4=y
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# CONFIG_VPL_LZMA is not set
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CONFIG_ERRNO_STR=y
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