arm: rockchip: Add RK3576 arch core support
The Rockchip RK3576 is a ARM-based SoC with quad-core Cortex-A72 and quad-core Cortex-A53 including 6TOPS NPU, Mali-G52 MC3, HDMI Out, DP, eDP, MIPI DSI, MIPI CSI2, LPDDR4/4X/5, eMMC5.1, SD3.0/MMC4.5, UFS, USB OTG 3.0, Type-C, USB 2.0, PCIe 2.1, SATA 3, Ethernet, SDIO3.0, I2C, UART, SPI, GPIO and PWM. Add arch core support for it. Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com> [adapted for mainline u-boot] Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Xuhui Lin
Simon Glass
131
arch/arm/dts/rk3576-u-boot.dtsi
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131
arch/arm/dts/rk3576-u-boot.dtsi
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@@ -0,0 +1,131 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* (C) Copyright 2025 Rockchip Electronics Co., Ltd
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*/
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#include "rockchip-u-boot.dtsi"
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/ {
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chosen {
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u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
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};
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dmc {
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compatible = "rockchip,rk3576-dmc";
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bootph-all;
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};
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};
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&cru {
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bootph-all;
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};
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&emmc_bus8 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&emmc_clk {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&emmc_cmd {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&emmc_rstnout {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&emmc_strb {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&ioc_grf {
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bootph-all;
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};
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&pcfg_pull_none {
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bootph-all;
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};
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&pcfg_pull_up {
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bootph-all;
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};
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&pcfg_pull_up_drv_level_2 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&pcfg_pull_up_drv_level_3 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&pinctrl {
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bootph-all;
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};
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&pmu1_grf {
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bootph-all;
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};
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&sdhci {
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bootph-pre-ram;
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bootph-some-ram;
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u-boot,spl-fifo-mode;
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};
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&sdmmc {
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bootph-pre-ram;
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bootph-some-ram;
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u-boot,spl-fifo-mode;
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};
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&sdmmc0_bus4 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&sdmmc0_clk {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&sdmmc0_cmd {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&sdmmc0_det {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&sdmmc0_pwren {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&sys_grf {
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bootph-all;
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};
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&uart0 {
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bootph-all;
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clock-frequency = <24000000>;
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};
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&uart0m0_xfer {
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bootph-pre-sram;
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bootph-pre-ram;
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};
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&xin24m {
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bootph-all;
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};
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11
arch/arm/include/asm/arch-rk3576/boot0.h
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11
arch/arm/include/asm/arch-rk3576/boot0.h
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@@ -0,0 +1,11 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2021 Rockchip Electronics Co., Ltd
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*/
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#ifndef __ASM_ARCH_BOOT0_H__
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#define __ASM_ARCH_BOOT0_H__
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#include <asm/arch-rockchip/boot0.h>
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#endif
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11
arch/arm/include/asm/arch-rk3576/gpio.h
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11
arch/arm/include/asm/arch-rk3576/gpio.h
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@@ -0,0 +1,11 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2021 Rockchip Electronics Co., Ltd
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*/
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#ifndef __ASM_ARCH_GPIO_H__
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#define __ASM_ARCH_GPIO_H__
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#include <asm/arch-rockchip/gpio.h>
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#endif
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@@ -403,6 +403,56 @@ config ROCKCHIP_RK3568
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and video codec support. Peripherals include Gigabit Ethernet,
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USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
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config ROCKCHIP_RK3576
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bool "Support Rockchip RK3576"
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select ARM64
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select SUPPORT_SPL
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select SPL
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select CLK
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select PINCTRL
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select RAM
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select REGMAP
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select SYSCON
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select BOARD_LATE_INIT
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select DM_REGULATOR_FIXED
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select DM_RESET
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imply ARMV8_CRYPTO
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imply ARMV8_SET_SMPEN
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imply BOOTSTD_FULL
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imply DM_RNG
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imply FIT
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imply LEGACY_IMAGE_FORMAT
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imply MISC
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imply MISC_INIT_R
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imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP
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imply OF_LIBFDT_OVERLAY
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imply OF_LIVE
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imply OF_UPSTREAM
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imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP
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imply RNG_ROCKCHIP
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imply ROCKCHIP_COMMON_BOARD
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imply ROCKCHIP_COMMON_STACK_ADDR
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imply ROCKCHIP_EXTERNAL_TPL
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imply ROCKCHIP_OTP
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imply SPL_ATF
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imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
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imply SPL_CLK
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imply SPL_DM_SEQ_ALIAS
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imply SPL_FIT_SIGNATURE
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imply SPL_LOAD_FIT
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imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
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imply SPL_OF_CONTROL
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imply SPL_PINCTRL
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imply SPL_RAM
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imply SPL_REGMAP
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imply SPL_SERIAL
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imply SPL_SYSCON
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imply SYS_RELOC_GD_ENV_ADDR
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imply SYSRESET
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help
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The Rockchip RK3576 is a ARM-based SoC with quad-core Cortex-A72 and
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and quad-core Cortex-A53.
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config ROCKCHIP_RK3588
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bool "Support Rockchip RK3588"
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select ARM64
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@@ -691,6 +741,7 @@ source "arch/arm/mach-rockchip/rk3368/Kconfig"
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source "arch/arm/mach-rockchip/rk3399/Kconfig"
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source "arch/arm/mach-rockchip/rk3528/Kconfig"
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source "arch/arm/mach-rockchip/rk3568/Kconfig"
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source "arch/arm/mach-rockchip/rk3576/Kconfig"
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source "arch/arm/mach-rockchip/rk3588/Kconfig"
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source "arch/arm/mach-rockchip/rv1108/Kconfig"
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source "arch/arm/mach-rockchip/rv1126/Kconfig"
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@@ -44,6 +44,7 @@ obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/
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obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
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obj-$(CONFIG_ROCKCHIP_RK3528) += rk3528/
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obj-$(CONFIG_ROCKCHIP_RK3568) += rk3568/
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obj-$(CONFIG_ROCKCHIP_RK3576) += rk3576/
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obj-$(CONFIG_ROCKCHIP_RK3588) += rk3588/
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obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/
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obj-$(CONFIG_ROCKCHIP_RV1126) += rv1126/
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15
arch/arm/mach-rockchip/rk3576/Kconfig
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15
arch/arm/mach-rockchip/rk3576/Kconfig
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@@ -0,0 +1,15 @@
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if ROCKCHIP_RK3576
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config ROCKCHIP_BOOT_MODE_REG
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default 0x26024040
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config ROCKCHIP_STIMER_BASE
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default 0x27400000
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config SYS_SOC
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default "rk3576"
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config SYS_CONFIG_NAME
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default "rk3576_common"
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endif
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9
arch/arm/mach-rockchip/rk3576/Makefile
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9
arch/arm/mach-rockchip/rk3576/Makefile
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@@ -0,0 +1,9 @@
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#
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# (C) Copyright 2023 Rockchip Electronics Co., Ltd
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += rk3576.o
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obj-y += clk_rk3576.o
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obj-y += syscon_rk3576.o
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18
arch/arm/mach-rockchip/rk3576/clk_rk3576.c
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18
arch/arm/mach-rockchip/rk3576/clk_rk3576.c
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@@ -0,0 +1,18 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* (C) Copyright 2020 Rockchip Electronics Co., Ltd.
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*/
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#include <dm.h>
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#include <asm/arch-rockchip/cru_rk3576.h>
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int rockchip_get_clk(struct udevice **devp)
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{
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return uclass_get_device_by_driver(UCLASS_CLK,
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DM_DRIVER_GET(rockchip_rk3576_cru), devp);
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}
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void *rockchip_get_cru(void)
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{
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return (void *)RK3576_CRU_BASE;
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}
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155
arch/arm/mach-rockchip/rk3576/rk3576.c
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155
arch/arm/mach-rockchip/rk3576/rk3576.c
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@@ -0,0 +1,155 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2024 Rockchip Electronics Co., Ltd
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*/
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#include <asm/armv8/mmu.h>
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#include <asm/arch-rockchip/bootrom.h>
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#include <asm/arch-rockchip/hardware.h>
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#define SYS_GRF_BASE 0x2600A000
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#define SYS_GRF_SOC_CON2 0x0008
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#define SYS_GRF_SOC_CON7 0x001c
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#define SYS_GRF_SOC_CON11 0x002c
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#define SYS_GRF_SOC_CON12 0x0030
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#define GPIO0_IOC_BASE 0x26040000
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#define GPIO0B_PULL_L 0x0024
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#define GPIO0B_IE_L 0x002C
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#define SYS_SGRF_BASE 0x26004000
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#define SYS_SGRF_SOC_CON14 0x0058
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#define SYS_SGRF_SOC_CON15 0x005C
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#define SYS_SGRF_SOC_CON20 0x0070
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#define FW_SYS_SGRF_BASE 0x26005000
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#define SGRF_DOMAIN_CON1 0x4
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#define SGRF_DOMAIN_CON2 0x8
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#define SGRF_DOMAIN_CON3 0xc
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#define SGRF_DOMAIN_CON4 0x10
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#define SGRF_DOMAIN_CON5 0x14
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const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
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[BROM_BOOTSOURCE_EMMC] = "/soc/mmc@2a330000",
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[BROM_BOOTSOURCE_SD] = "/soc/mmc@2a310000",
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};
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static struct mm_region rk3576_mem_map[] = {
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{
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/* I/O area */
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.virt = 0x20000000UL,
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.phys = 0x20000000UL,
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.size = 0xb080000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* PMU_SRAM, CBUF, SYSTEM_SRAM */
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.virt = 0x3fe70000UL,
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.phys = 0x3fe70000UL,
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.size = 0x190000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* MSCH_DDR_PORT */
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.virt = 0x40000000UL,
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.phys = 0x40000000UL,
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.size = 0x400000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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/* PCIe 0+1 */
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.virt = 0x900000000UL,
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.phys = 0x900000000UL,
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.size = 0x100800000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = rk3576_mem_map;
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void board_debug_uart_init(void)
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{
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}
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#define HP_TIMER_BASE CONFIG_ROCKCHIP_STIMER_BASE
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#define HP_CTRL_REG 0x04
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#define TIMER_EN BIT(0)
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#define HP_LOAD_COUNT0_REG 0x14
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#define HP_LOAD_COUNT1_REG 0x18
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void rockchip_stimer_init(void)
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{
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u32 reg;
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if (!IS_ENABLED(CONFIG_XPL_BUILD))
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return;
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reg = readl(HP_TIMER_BASE + HP_CTRL_REG);
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if (reg & TIMER_EN)
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return;
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asm volatile("msr cntfrq_el0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY));
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writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT0_REG);
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writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT1_REG);
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writel((TIMER_EN << 16) | TIMER_EN, HP_TIMER_BASE + HP_CTRL_REG);
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}
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int arch_cpu_init(void)
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{
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u32 val;
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if (!IS_ENABLED(CONFIG_SPL_BUILD))
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return 0;
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/* Set the emmc to access ddr memory */
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val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON2);
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writel(val | 0x7, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON2);
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/* Set the sdmmc0 to access ddr memory */
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val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON5);
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writel(val | 0x700, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON5);
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/* Set the UFS to access ddr memory */
|
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val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON3);
|
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writel(val | 0x70000, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON3);
|
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|
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/* Set the fspi0 and fspi1 to access ddr memory */
|
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val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON4);
|
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writel(val | 0x7700, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON4);
|
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/* Set the decom to access ddr memory */
|
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val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON1);
|
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writel(val | 0x700, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON1);
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/*
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* Set the GPIO0B0~B3 pull up and input enable.
|
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* Keep consistent with other IO.
|
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*/
|
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writel(0x00ff00ff, GPIO0_IOC_BASE + GPIO0B_PULL_L);
|
||||
writel(0x000f000f, GPIO0_IOC_BASE + GPIO0B_IE_L);
|
||||
|
||||
/*
|
||||
* Set SYS_GRF_SOC_CON2[12](input of pwm2_ch0) as 0,
|
||||
* keep consistent with other pwm.
|
||||
*/
|
||||
writel(0x10000000, SYS_GRF_BASE + SYS_GRF_SOC_CON2);
|
||||
|
||||
/* Enable noc slave response timeout */
|
||||
writel(0x80008000, SYS_GRF_BASE + SYS_GRF_SOC_CON11);
|
||||
writel(0xffffffe0, SYS_GRF_BASE + SYS_GRF_SOC_CON12);
|
||||
|
||||
/*
|
||||
* Enable cci channels for below module AXI R/W
|
||||
* Module: GMAC0/1, MMU0/1(PCIe, SATA, USB3)
|
||||
*/
|
||||
writel(0xffffff00, SYS_SGRF_BASE + SYS_SGRF_SOC_CON20);
|
||||
|
||||
return 0;
|
||||
}
|
||||
22
arch/arm/mach-rockchip/rk3576/syscon_rk3576.c
Normal file
22
arch/arm/mach-rockchip/rk3576/syscon_rk3576.c
Normal file
@@ -0,0 +1,22 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* (C) Copyright 2023 Rockchip Electronics Co., Ltd
|
||||
*/
|
||||
|
||||
#include <dm.h>
|
||||
#include <asm/arch-rockchip/clock.h>
|
||||
|
||||
static const struct udevice_id rk3576_syscon_ids[] = {
|
||||
{ .compatible = "rockchip,rk3576-sys-grf", .data = ROCKCHIP_SYSCON_GRF },
|
||||
{ .compatible = "rockchip,rk3576-pmu1-grf", .data = ROCKCHIP_SYSCON_PMUGRF },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(rockchip_rk3576_syscon) = {
|
||||
.name = "rockchip_rk3576_syscon",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = rk3576_syscon_ids,
|
||||
#if CONFIG_IS_ENABLED(OF_REAL)
|
||||
.bind = dm_scan_fdt_dev,
|
||||
#endif
|
||||
};
|
||||
@@ -110,6 +110,7 @@ static int rockchip_dram_init_banksize(void)
|
||||
u8 i, j;
|
||||
|
||||
if (!IS_ENABLED(CONFIG_ROCKCHIP_RK3588) &&
|
||||
!IS_ENABLED(CONFIG_ROCKCHIP_RK3576) &&
|
||||
!IS_ENABLED(CONFIG_ROCKCHIP_RK3568) &&
|
||||
!IS_ENABLED(CONFIG_ROCKCHIP_RK3528))
|
||||
return -ENOTSUPP;
|
||||
|
||||
@@ -281,6 +281,15 @@ To build rk3568 boards:
|
||||
make evb-rk3568_defconfig
|
||||
make CROSS_COMPILE=aarch64-linux-gnu-
|
||||
|
||||
To build rk3576 boards:
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
export BL31=../rkbin/bin/rk35/rk3576_bl31_v1.04.elf
|
||||
export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3576_ddr_lp4_2112MHz_lp5_2736MHz_v1.03.bin
|
||||
make roc-pc-rk3576_defconfig
|
||||
make CROSS_COMPILE=aarch64-linux-gnu-
|
||||
|
||||
To build rk3588 boards:
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
41
include/configs/rk3576_common.h
Normal file
41
include/configs/rk3576_common.h
Normal file
@@ -0,0 +1,41 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2024 Rockchip Electronics Co., Ltd
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_RK3576_COMMON_H
|
||||
#define __CONFIG_RK3576_COMMON_H
|
||||
|
||||
#define CFG_CPUID_OFFSET 0xa
|
||||
|
||||
#include "rockchip-common.h"
|
||||
|
||||
#define CFG_IRAM_BASE 0x3ff80000
|
||||
|
||||
#define CFG_SYS_SDRAM_BASE 0x40000000
|
||||
/* Used by board_get_usable_ram_top(), space below the 4G address boundary */
|
||||
#define SDRAM_MAX_SIZE (SZ_4G - CFG_SYS_SDRAM_BASE)
|
||||
|
||||
#ifndef ROCKCHIP_DEVICE_SETTINGS
|
||||
#define ROCKCHIP_DEVICE_SETTINGS
|
||||
#endif
|
||||
|
||||
#define ENV_MEM_LAYOUT_SETTINGS \
|
||||
"scriptaddr=0x40c00000\0" \
|
||||
"script_offset_f=0xffe000\0" \
|
||||
"script_size_f=0x2000\0" \
|
||||
"pxefile_addr_r=0x40e00000\0" \
|
||||
"kernel_addr_r=0x42000000\0" \
|
||||
"kernel_comp_addr_r=0x4a000000\0" \
|
||||
"fdt_addr_r=0x52000000\0" \
|
||||
"fdtoverlay_addr_r=0x52100000\0" \
|
||||
"ramdisk_addr_r=0x52180000\0" \
|
||||
"kernel_comp_size=0x8000000\0"
|
||||
|
||||
#define CFG_EXTRA_ENV_SETTINGS \
|
||||
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
|
||||
ENV_MEM_LAYOUT_SETTINGS \
|
||||
ROCKCHIP_DEVICE_SETTINGS \
|
||||
"boot_targets=" BOOT_TARGETS "\0"
|
||||
|
||||
#endif /* __CONFIG_RK3576_COMMON_H */
|
||||
Reference in New Issue
Block a user