rockchip: Set the skip-at-start property correctly

The rockchip image is written to the media at block 64, which is a 32K
offset, so set the skip-at-start property to 0x8000

Update CONFIG_SPL_PAD_TO to point to the offset in the image, since
Binman is dealing with the 'missing' 32K now.

Series-changes: 2
- Move this patch to the end of the series
- Drop 0x8000 offset for SPI

Series-changes: 5
- Add to VPL file also

Series-changes: 6
- Update CONFIG_SPL_PAD_TO for puma-rk3399 and ringneck-px30

Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass
2025-01-29 06:56:10 -07:00
parent 7ffcf24660
commit 768b87d25b
5 changed files with 5 additions and 3 deletions

View File

@@ -171,6 +171,7 @@
simple-bin { simple-bin {
filename = "u-boot-rockchip.bin"; filename = "u-boot-rockchip.bin";
pad-byte = <0xff>; pad-byte = <0xff>;
skip-at-start = <0x8000>;
mkimage { mkimage {
filename = "idbloader.img"; filename = "idbloader.img";

View File

@@ -113,6 +113,7 @@
simple-bin { simple-bin {
filename = "u-boot-rockchip.bin"; filename = "u-boot-rockchip.bin";
pad-byte = <0xff>; pad-byte = <0xff>;
skip-at-start = <0x8000>;
alternates-fdt { alternates-fdt {
fdt-list-dir = "dts/upstream/src/arm64/rockchip"; fdt-list-dir = "dts/upstream/src/arm64/rockchip";

View File

@@ -97,7 +97,7 @@ config SPL_MAX_SIZE
config SPL_PAD_TO config SPL_PAD_TO
hex "Offset to which the SPL should be padded before appending the SPL payload" hex "Offset to which the SPL should be padded before appending the SPL payload"
default 0x7f8000 if ARCH_ROCKCHIP default 0x800000 if ARCH_ROCKCHIP
default 0x31000 if ARCH_MX6 && MX6_OCRAM_256KB default 0x31000 if ARCH_MX6 && MX6_OCRAM_256KB
default 0x11000 if ARCH_MX7 || (ARCH_MX6 && !MX6_OCRAM_256KB) default 0x11000 if ARCH_MX7 || (ARCH_MX6 && !MX6_OCRAM_256KB)
default 0x10000 if ARCH_KEYSTONE default 0x10000 if ARCH_KEYSTONE

View File

@@ -23,7 +23,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb"
CONFIG_CONSOLE_MUX=y CONFIG_CONSOLE_MUX=y
CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_MAX_SIZE=0x2e000
CONFIG_SPL_PAD_TO=0x38000 CONFIG_SPL_PAD_TO=0x40000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
CONFIG_SPL_I2C=y CONFIG_SPL_I2C=y

View File

@@ -26,7 +26,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/px30-ringneck-haikou.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_MAX_SIZE=0x20000
CONFIG_SPL_PAD_TO=0x38000 CONFIG_SPL_PAD_TO=0x40000
CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set