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ram: renesas: Add Renesas R-Car Gen4 DBSC5 driver

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Add Renesas R-Car Gen4 DBSC5 DRAM controller driver. This driver is currently
capable of bringing LPDDR5 DRAM on Renesas R-Car V4H Whitehawk board. Further
boards can be supported by supplying board specific DRAM configuration data
via dbsc5_get_board_data(). Support for R-Car V4M is not implemented, however
the driver is already mostly prepared to support this SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
(cherry picked from commit 7366aacf8e)
This commit is contained in:
Marek Vasut
2024-12-12 14:34:30 +01:00
committed by Simon Glass
parent 0c590f80b5
commit 88df1859be
9 changed files with 5382 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/ram/Kconfig
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@@ -129,6 +129,7 @@ config K3_INLINE_ECC
source "drivers/ram/aspeed/Kconfig"
source "drivers/ram/cadence/Kconfig"
source "drivers/ram/octeon/Kconfig"
source "drivers/ram/renesas/Kconfig"
source "drivers/ram/rockchip/Kconfig"
source "drivers/ram/sifive/Kconfig"
source "drivers/ram/stm32mp1/Kconfig"

7
drivers/ram/renesas/Kconfig Normal file
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@@ -0,0 +1,7 @@
config RAM_RENESAS_DBSC5
bool "Renesas R-Car V4H/V4M DBSC5 controller driver"
depends on SPL && RAM && (R8A779G0 || R8A779H0)
default n
help
Enable this to support the DBSC5 DRAM controller initialization
on Renesas R8A779G0/R8A779H0 SoCs.

3
drivers/ram/renesas/Makefile
View File

@@ -1,3 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_RAM_RENESAS_DBSC5) += dbsc5/
endif
obj-$(CONFIG_RZN1) += rzn1/

3
drivers/ram/renesas/dbsc5/Makefile Normal file
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@@ -0,0 +1,3 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y += dbsc5.o dram.o qos.o rtvram.o

79
drivers/ram/renesas/dbsc5/dbsc5.c Normal file
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@@ -0,0 +1,79 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2024 Renesas Electronics Corp.
*/
#include <asm/io.h>
#include <dm.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <errno.h>
#include <linux/sizes.h>
#include <ram.h>
#include "dbsc5.h"
static int renesas_dbsc5_probe(struct udevice *dev)
{
struct udevice *pdev;
int ret;
ret = uclass_get_device_by_name(UCLASS_RAM, "dbsc5_dram", &pdev);
if (ret)
return ret;
ret = uclass_get_device_by_name(UCLASS_NOP, "dbsc5_qos", &pdev);
if (ret)
return ret;
return 0;
}
int renesas_dbsc5_bind(struct udevice *dev)
{
struct udevice *ramdev, *qosdev;
struct driver *ramdrv, *qosdrv;
int ret;
ramdrv = lists_driver_lookup_name("dbsc5_dram");
if (!ramdrv)
return -ENOENT;
qosdrv = lists_driver_lookup_name("dbsc5_qos");
if (!qosdrv)
return -ENOENT;
ret = device_bind_with_driver_data(dev, ramdrv, "dbsc5_dram",
dev_get_driver_data(dev),
dev_ofnode(dev), &ramdev);
if (ret)
return ret;
ret = device_bind_with_driver_data(dev, qosdrv, "dbsc5_qos", 0,
dev_ofnode(dev), &qosdev);
if (ret)
device_unbind(ramdev);
return ret;
}
struct renesas_dbsc5_data r8a779g0_dbsc5_data = {
.clock_node = "renesas,r8a779g0-cpg-mssr",
.reset_node = "renesas,r8a779g0-rst"
};
static const struct udevice_id renesas_dbsc5_ids[] = {
{
.compatible = "renesas,r8a779g0-dbsc",
.data = (ulong)&r8a779g0_dbsc5_data
},
{ /* sentinel */ }
};
U_BOOT_DRIVER(renesas_dbsc5) = {
.name = "dbsc5",
.id = UCLASS_NOP,
.of_match = renesas_dbsc5_ids,
.bind = renesas_dbsc5_bind,
.probe = renesas_dbsc5_probe,
};

28
drivers/ram/renesas/dbsc5/dbsc5.h Normal file
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@@ -0,0 +1,28 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2024 Renesas Electronics Corp.
*/
#ifndef __DRIVERS_RAM_RENESAS_DBSC5_DBSC5_H__
#define __DRIVERS_RAM_RENESAS_DBSC5_DBSC5_H__
/*
* DBSC5 ... 0xe678_0000..0xe67fffff
* - AXMM_BASE 0xe6780000 MM (DDR Hier) MM AXI Router - Region 0
* - DBSC_A_BASE 0xe6790000 MM (DDR Hier) DBSC0A - Region 0
* - CCI_BASE 0xe67A0000 MM (DDR Hier) FBA for MM
* - DBSC_D_BASE 0xE67A4000 MM (DDR Hier) DBSC0D - Region 0
* - QOS_BASE 0xe67E0000 MM (DDR Hier) M-STATQ (64kiB)
*/
#define DBSC5_AXMM_OFFSET 0x00000
#define DBSC5_DBSC_A_OFFSET 0x10000
#define DBSC5_CCI_OFFSET 0x20000
#define DBSC5_DBSC_D_OFFSET 0x24000
#define DBSC5_QOS_OFFSET 0x60000
struct renesas_dbsc5_data {
const char *clock_node;
const char *reset_node;
};
#endif /* __DRIVERS_RAM_RENESAS_DBSC5_DBSC5_H__ */

4532
drivers/ram/renesas/dbsc5/dram.c Normal file
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File diff suppressed because it is too large Load Diff

636
drivers/ram/renesas/dbsc5/qos.c Normal file
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@@ -0,0 +1,636 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2024 Renesas Electronics Corp.
*/
#include <asm/io.h>
#include <dm.h>
#include <errno.h>
#include <hang.h>
#include <linux/sizes.h>
#include <ram.h>
#include "dbsc5.h"
/* AXMM */
#define AXMM_ADSPLCR0 0x4008
#define AXMM_ADSPLCR1 0x400C
#define AXMM_ADSPLCR2 0x4010
#define AXMM_ADSPLCR3 0x4014
#define AXMM_MMCR 0x4300
#define AXMM_TR0CR0 0x51000
#define AXMM_TR1CR0 0x51004
#define AXMM_TR2CR0 0x51008
#define AXMM_TR3CR 0x5100C
#define AXMM_TR3CR0 0x5100C
#define AXMM_TR0CR1 0x51100
#define AXMM_TR1CR1 0x51104
#define AXMM_TR2CR1 0x51108
#define AXMM_TR3CR1 0x5110C
#define AXMM_TR0CR2 0x51200
#define AXMM_TR1CR2 0x51204
#define AXMM_TR2CR2 0x51208
#define AXMM_TR3CR2 0x5120C
#define ACTEXT_RT0_R 0xFFC50800
#define ACTEXT_RT0_W 0xFFC51800
#define ACTEXT_IR0_R 0xFF890800
#define ACTEXT_IR0_W 0xFF891800
#define ACTEXT_IR1_R 0xFF892800
#define ACTEXT_IR1_W 0xFF893800
#define SI0_RW_MAX 0xF1201110
#define SI1_RW_MAX 0xF1202110
/* DBSC */
#define DBSC_A_CH_OFFSET 0x8000
#define DBSC_D_CH_OFFSET 0x4000
#define DBSC_SYSCNT0 0x0100
#define DBSC_SYSCNT1 0x0104
#define DBSC_FCPRSCTRL 0x0110
#define DBSC_DBBUS0CNF2 0x0808
#define DBSC_DBCAM0CNF1 0x0904
#define DBSC_DBCAM0CNF2 0x0908
#define DBSC_DBCAM0CNF3 0x090C
#define DBSC_DBCAMDIS 0x09FC
#define DBSC_DBSCHCNT0 0x1000
#define DBSC_DBSCHSZ0 0x1010
#define DBSC_DBSCHRW0 0x1020
#define DBSC_SCFCTST2 0x1048
#define DBSC_DBSCHQOS_0_0 0x1100
#define DBSC_DBSCHQOS_0_1 0x1104
#define DBSC_DBSCHQOS_0_2 0x1108
#define DBSC_DBSCHQOS_0_3 0x110C
#define DBSC_DBSCHQOS_4_0 0x1140
#define DBSC_DBSCHQOS_4_1 0x1144
#define DBSC_DBSCHQOS_4_2 0x1148
#define DBSC_DBSCHQOS_4_3 0x114C
#define DBSC_DBSCHQOS_9_0 0x1190
#define DBSC_DBSCHQOS_9_1 0x1194
#define DBSC_DBSCHQOS_9_2 0x1198
#define DBSC_DBSCHQOS_9_3 0x119C
#define DBSC_DBSCHQOS_12_0 0x11C0
#define DBSC_DBSCHQOS_12_1 0x11C4
#define DBSC_DBSCHQOS_12_2 0x11C8
#define DBSC_DBSCHQOS_12_3 0x11CC
#define DBSC_DBSCHQOS_13_0 0x11D0
#define DBSC_DBSCHQOS_13_1 0x11D4
#define DBSC_DBSCHQOS_13_2 0x11D8
#define DBSC_DBSCHQOS_13_3 0x11DC
#define DBSC_DBSCHQOS_14_0 0x11E0
#define DBSC_DBSCHQOS_14_1 0x11E4
#define DBSC_DBSCHQOS_14_2 0x11E8
#define DBSC_DBSCHQOS_14_3 0x11EC
#define DBSC_DBSCHQOS_15_0 0x11F0
#define DBSC_DBSCHQOS_15_1 0x11F4
#define DBSC_DBSCHQOS_15_2 0x11F8
#define DBSC_DBSCHQOS_15_3 0x11FC
/* CCI */
#define CCIQOS00 0xC020
#define CCIQOS01 0xC024
#define CCIQOS10 0xD000
#define CCIQOS11 0xD004
/* QOS */
#define QOS_FIX_QOS_BANK0 0x0
#define QOS_FIX_QOS_BANK1 0x1000
#define QOS_BE_QOS_BANK0 0x2000
#define QOS_BE_QOS_BANK1 0x3000
#define QOS_SL_INIT 0x8000
#define QOS_REF_ARS 0x8004
#define QOS_STATQC 0x8008
#define QOS_REF_ENBL 0x8044
#define QOS_BWG 0x804C
#define QOS_RAS 0x10000
#define QOS_FSS 0x10048
#define QOS_RAEN 0x10018
#define QOS_DANN_LOW 0x10030
#define QOS_DANN_HIGH 0x10034
#define QOS_DANT 0x10038
#define QOS_EMS_LOW 0x10040
#define QOS_EMS_HIGH 0x10044
#define QOS_INSFC 0x10050
#define QOS_EARLYR 0x10060
#define QOS_RACNT0 0x10080
#define QOS_STATGEN0 0x10088
#define QOSWT_FIX_QOS_BANK0 0x800
#define QOSWT_FIX_QOS_BANK1 0x1800
#define QOSWT_BE_QOS_BANK0 0x2800
#define QOSWT_BE_QOS_BANK1 0x3800
#define QOSWT_WTEN 0x8030
#define QOSWT_WTREF 0x8034
#define QOSWT_WTSET0 0x8038
#define QOSWT_WTSET1 0x803C
static const struct {
u64 fix;
u64 be;
} g_qosbw_tbl[] = {
{ 0x000C04010000FFFF, 0x00200030004FFC01 },
{ 0x000C04010000FFFF, 0x00100030004FFC01 },
{ 0x000C04010000FFFF, 0x00100030004FFC01 },
{ 0x000C04010000FFFF, 0x00200030004FFC01 },
{ 0x000C04010000FFFF, 0x00100030004FFC01 },
{ 0x000C04010000FFFF, 0x00100030004FFC01 },
{ 0x000C04010000FFFF, 0x00100030004FFC01 },
{ 0x000C04010000FFFF, 0x00100030004FFC01 },
{ 0x000C04010000FFFF, 0x00100030004FFC01 },
{ 0x000C04010000FFFF, 0x00200030004FFC01 },
{ 0x000C04010000FFFF, 0x0000000000000000 },
{ 0x000C04080000FFFF, 0x00200030004FFC01 },
{ 0x000C04080000FFFF, 0x00100030004FFC01 },
{ 0x000C04080000FFFF, 0x00100030004FFC01 },
{ 0x000C04080000FFFF, 0x00100030004FFC01 },
{ 0x000C04010000FFFF, 0x00200030004FFC01 },
{ 0x000C04080000FFFF, 0x00100030004FFC01 },
{ 0x000C04080000FFFF, 0x00100030004FFC01 },
{ 0x000C04080000FFFF, 0x00100030004FFC01 },
{ 0x000C04080000FFFF, 0x00100030004FFC01 },
{ 0x000C04100000FFFF, 0x00100030004FFC01 },
{ 0x000C04100000FFFF, 0x00100030004FFC01 },
{ 0x000C04100000FFFF, 0x0000000000000000 },
{ 0x000C08140000FFFF, 0x00100030004FFC01 },
{ 0x000C08140000FFFF, 0x00100030004FFC01 },
{ 0x000000000000FFF0, 0x0000000000000000 },
{ 0x000C04100000FFFF, 0x00100030004FFC01 },
{ 0x000C04100000FFFF, 0x00100030004FFC01 },
{ 0x000C04100000FFFF, 0x0000000000000000 },
{ 0x000C04080000FFFF, 0x00100030004FFC01 },
{ 0x000C08140000FFFF, 0x00100030004FFC01 },
{ 0x000000000000FFFF, 0x0000000000000000 },
{ 0x000C04080000FFFF, 0x00100030004FFC01 },
{ 0x000C04080000FFFF, 0x00100030004FFC01 },
{ 0x000C04080000FFFF, 0x00100030004FFC01 },
{ 0x000C04080000FFFF, 0x00100030004FFC01 },
{ 0x000C04080000FFFF, 0x00100030004FFC01 },
{ 0x000C04080000FFFF, 0x00100030004FFC01 },
{ 0x001404080000FFFF, 0x00100030004FFC01 },
{ 0x001404080000FFFF, 0x00100030004FFC01 },
{ 0x000C04010000FFFF, 0x001000F0004FFC01 },
{ 0x000C04010000FFFF, 0x001000F0004FFC01 },
{ 0x000C04010000FFFF, 0x002000F0004FFC01 },
{ 0x000C04010000FFFF, 0x002000F0004FFC01 },
{ 0x000000000000FFFF, 0x0000000000000000 },
{ 0x000000000000FFFF, 0x0000000000000000 },
{ 0x000000000000FFFF, 0x0000000000000000 },
{ 0x000000000000FFFF, 0x0000000000000000 },
{ 0x000C144F0000FFFF, 0x00100030004FFC01 },
{ 0x000C144F0000FFFF, 0x00100030004FFC01 },
{ 0x000C144F0000FFFF, 0x00100030004FFC01 },
{ 0x000C144F0000FFFF, 0x00100030004FFC01 },
{ 0x000C144F0000FFFF, 0x00100030004FFC01 },
{ 0x000C144F0000FFFF, 0x00100030004FFC01 },
{ 0x000000000000FFFF, 0x0000000000000000 },
{ 0x000C144F0000FFFF, 0x00100030004FFC01 },
{ 0x000000000000FFFF, 0x0000000000000000 },
{ 0x000C144F0000FFFF, 0x00100030004FFC01 },
{ 0x000000000000FFFF, 0x0000000000000000 },
{ 0x000C144F0000FFFF, 0x00100030004FFC01 },
{ 0x000000000000FFFF, 0x0000000000000000 },
{ 0x000000000000FFFF, 0x0000000000000000 },
{ 0x000C144F0000FFFF, 0x00100030004FFC01 },
{ 0x000C144F0000FFFF, 0x00100030004FFC01 },
{ 0x000C04200000FFFF, 0x00100030004FFC01 },
{ 0x000C04100000FFFF, 0x00100030004FFC01 },
{ 0x000C144F0000FFFF, 0x00100030004FFC01 },
{ 0x000C144F0000FFFF, 0x00100030004FFC01 },
{ 0x000C0C4F0000FFFF, 0x00100030004FFC01 },
{ 0x000C0C4F0000FFFF, 0x00100030004FFC01 },
{ 0x001404080000FFFF, 0x00100030004FFC01 },
{ 0x000C04080000FFFF, 0x00100030004FFC01 },
{ 0x000C04080000FFFF, 0x00100030004FFC01 },
{ 0x000C04010000FFFF, 0x00100030004FFC01 },
{ 0x001424870000FFFF, 0x00100030004FFC01 },
{ 0x001424870000FFFF, 0x00100030004FFC01 },
{ 0x000C149E0000FFFF, 0x00100030004FFC01 },
{ 0x000C149E0000FFFF, 0x00100030004FFC01 },
{ 0x000000000000FFFF, 0x0000000000000000 },
{ 0x000000000000FFFF, 0x0000000000000000 },
{ 0x00140C050000FFFF, 0x00100030004FFC01 },
{ 0x0014450E0000FFFF, 0x00100030004FFC01 },
{ 0x001424870000FFFF, 0x00100030004FFC01 },
{ 0x0014289E0000FFFF, 0x00000000000FFC00 },
{ 0x0014289E0000FFFF, 0x00000000000FFC00 },
{ 0x0014149E0000FFFF, 0x0000000000000000 },
{ 0x000000000000FFFF, 0x0000000000000000 },
{ 0x000000000000FFFF, 0x0000000000000000 },
{ 0x001004080000FFFF, 0x0000000000000000 },
{ 0x001004080000FFFF, 0x0000000000000000 },
{ 0x001004080000FFFF, 0x0000000000000000 },
{ 0x000C00000000FFFF, 0x001000F0004FFC01 },
{ 0x000C00000000FFFF, 0x001000F0004FFC01 },
{ 0x000C04080000FFFF, 0x00100030004FFC01 },
{ 0x000C04080000FFFF, 0x00100030004FFC01 },
{ 0x000000000000FFFF, 0x0000000000000000 },
{ 0x000C04080000FFFF, 0x00100030004FFC01 },
{ 0x000C04080000FFFF, 0x00100030004FFC01 },
{ 0x000C04080000FFFF, 0x00100030004FFC01 },
{ 0x000000000000FFFF, 0x0000000000000000 },
{ 0x000C04080000FFFF, 0x00100030004FFC01 },
{ 0x001404080000FFFF, 0x00100030004FFC01 },
{ 0x000C04080000FFFF, 0x00100030004FFC01 },
{ 0x000C04080000FFFF, 0x00100030004FFC01 },
{ 0x000000000000FFFF, 0x0000000000000000 },
{ 0x000000000000FFFF, 0x0000000000000000 },
{ 0x000000000000FFFF, 0x0000000000000000 },
{ 0x000000000000FFFF, 0x0000000000000000 },
{ 0x000000000000FFFF, 0x0000000000000000 },
{ 0x000000000000FFFF, 0x0000000000000000 },
{ 0x000000000000FFFF, 0x0000000000000000 },
{ 0x000000000000FFFF, 0x0000000000000000 },
{ 0x000000000000FFFF, 0x0000000000000000 },
{ 0x000000000000FFFF, 0x0000000000000000 },
{ 0x000C04010000FFFF, 0x001001D0004FFC01 },
{ 0x000000000000FFFF, 0x0000000000000000 },
{ 0x000C04010000FFFF, 0x001001D0004FFC01 },
{ 0x000000000000FFFF, 0x0000000000000000 },
{ 0x000C04010000FFFF, 0x001001D0004FFC01 },
{ 0x000C04010000FFFF, 0x00100030004FFC01 },
{ 0x000C04010000FFFF, 0x00100030004FFC01 },
{ 0x000C04010000FFFF, 0x001001D0004FFC01 },
{ 0x000C04010000FFFF, 0x00100030004FFC01 },
{ 0x000C04010000FFFF, 0x00100030004FFC01 },
{ 0x001404010000FFFF, 0x00100030004FFC01 }
};
static const struct {
u64 fix;
u64 be;
} g_qoswt_tbl[] = {
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x000C04050000FFFF, 0x0000000000000000 },
{ 0x000C080C0000FFFF, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x000C04050000C001, 0x0000000000000000 },
{ 0x000C080C0000C001, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x001424870000C001, 0x0000000000000000 },
{ 0x001424870000C001, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x001424870000FFFF, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 },
{ 0x0000000000000000, 0x0000000000000000 }
};
struct renesas_dbsc5_qos_priv {
void __iomem *regs;
};
static int dbsc5_qos_dbsc_setting(struct udevice *dev)
{
struct renesas_dbsc5_qos_priv *priv = dev_get_priv(dev);
void __iomem *regs_dbsc_a, *regs_dbsc_d;
unsigned int ch, nch;
if (IS_ENABLED(CONFIG_R8A779G0) &&
renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779G0)
nch = 2;
else if (IS_ENABLED(CONFIG_R8A779H0) &&
renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779H0)
nch = 1;
else
return -EINVAL;
for (ch = 0; ch < nch; ch++) {
regs_dbsc_a = priv->regs + DBSC5_DBSC_A_OFFSET + ch * DBSC_A_CH_OFFSET;
regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET + ch * DBSC_D_CH_OFFSET;
/* DBSC CAM, Scheduling Setting */
writel(0x1234, regs_dbsc_d + DBSC_SYSCNT0);
writel(0x1234, regs_dbsc_a + DBSC_SYSCNT0);
writel(0x48218, regs_dbsc_a + DBSC_DBCAM0CNF1);
writel(0x1C4, regs_dbsc_a + DBSC_DBCAM0CNF2);
writel(0x3, regs_dbsc_a + DBSC_DBCAM0CNF3);
if (IS_ENABLED(CONFIG_R8A779G0) &&
renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779G0 &&
(renesas_get_cpu_rev_integer() < 2 ||
(renesas_get_cpu_rev_integer() == 2 &&
renesas_get_cpu_rev_fraction() <= 1))) {
/* OTLINT-5579: V4H <= rev2.1 DBSC W/A-3 */
writel(0x11, regs_dbsc_a + DBSC_DBCAMDIS);
} else {
writel(0x10, regs_dbsc_a + DBSC_DBCAMDIS);
}
writel(0xF0037, regs_dbsc_a + DBSC_DBSCHCNT0);
writel(0x1, regs_dbsc_a + DBSC_DBSCHSZ0);
writel(0xF7311111, regs_dbsc_a + DBSC_DBSCHRW0);
writel(0x111F1FFF, regs_dbsc_a + DBSC_SCFCTST2);
/* OTLINT-5579: V4H DBSC WA3 */
writel(0x7, regs_dbsc_a + DBSC_DBBUS0CNF2);
/* DBSC QoS Setting */
writel(0xFFFF, regs_dbsc_a + DBSC_DBSCHQOS_0_0);
writel(0x480, regs_dbsc_a + DBSC_DBSCHQOS_0_1);
writel(0x300, regs_dbsc_a + DBSC_DBSCHQOS_0_2);
writel(0x180, regs_dbsc_a + DBSC_DBSCHQOS_0_3);
writel(0x400, regs_dbsc_a + DBSC_DBSCHQOS_4_0);
writel(0x300, regs_dbsc_a + DBSC_DBSCHQOS_4_1);
writel(0x200, regs_dbsc_a + DBSC_DBSCHQOS_4_2);
writel(0x100, regs_dbsc_a + DBSC_DBSCHQOS_4_3);
writel(0x300, regs_dbsc_a + DBSC_DBSCHQOS_9_0);
writel(0x240, regs_dbsc_a + DBSC_DBSCHQOS_9_1);
writel(0x180, regs_dbsc_a + DBSC_DBSCHQOS_9_2);
writel(0xC0, regs_dbsc_a + DBSC_DBSCHQOS_9_3);
writel(0x40, regs_dbsc_a + DBSC_DBSCHQOS_12_0);
writel(0x30, regs_dbsc_a + DBSC_DBSCHQOS_12_1);
writel(0x20, regs_dbsc_a + DBSC_DBSCHQOS_12_2);
writel(0x10, regs_dbsc_a + DBSC_DBSCHQOS_12_3);
writel(0x300, regs_dbsc_a + DBSC_DBSCHQOS_13_0);
writel(0x240, regs_dbsc_a + DBSC_DBSCHQOS_13_1);
writel(0x180, regs_dbsc_a + DBSC_DBSCHQOS_13_2);
writel(0xC0, regs_dbsc_a + DBSC_DBSCHQOS_13_3);
writel(0x200, regs_dbsc_a + DBSC_DBSCHQOS_14_0);
writel(0x180, regs_dbsc_a + DBSC_DBSCHQOS_14_1);
writel(0x100, regs_dbsc_a + DBSC_DBSCHQOS_14_2);
writel(0x80, regs_dbsc_a + DBSC_DBSCHQOS_14_3);
writel(0x100, regs_dbsc_a + DBSC_DBSCHQOS_15_0);
writel(0xC0, regs_dbsc_a + DBSC_DBSCHQOS_15_1);
writel(0x80, regs_dbsc_a + DBSC_DBSCHQOS_15_2);
writel(0x40, regs_dbsc_a + DBSC_DBSCHQOS_15_3);
/* Target register is only DBSC0 side. */
if (ch == 0)
writel(0x1, regs_dbsc_a + DBSC_FCPRSCTRL);
writel(0x1, regs_dbsc_a + DBSC_SYSCNT1);
writel(0x0, regs_dbsc_d + DBSC_SYSCNT0);
writel(0x0, regs_dbsc_a + DBSC_SYSCNT0);
}
return 0;
}
static int dbsc5_qos_settings_init(struct udevice *dev)
{
struct renesas_dbsc5_qos_priv *priv = dev_get_priv(dev);
void __iomem *regs_axmm = priv->regs + DBSC5_AXMM_OFFSET;
void __iomem *regs_cci = priv->regs + DBSC5_CCI_OFFSET;
void __iomem *regs_qos = priv->regs + DBSC5_QOS_OFFSET;
int i;
if (IS_ENABLED(CONFIG_R8A779G0) &&
renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779G0) {
/* Address Split 2ch */
writel(0x0, regs_axmm + AXMM_ADSPLCR0);
writel(0xFF1B0C, regs_axmm + AXMM_ADSPLCR1);
writel(0x0, regs_axmm + AXMM_ADSPLCR2);
writel(0x0, regs_axmm + AXMM_ADSPLCR3);
writel(0x8000000, regs_cci + CCIQOS00);
writel(0x8000000, regs_cci + CCIQOS01);
if (renesas_get_cpu_rev_integer() >= 2) {
writel(0x1, regs_cci + CCIQOS10);
writel(0x1, regs_cci + CCIQOS11);
} else {
writel(0x0, regs_cci + CCIQOS10);
writel(0x0, regs_cci + CCIQOS11);
}
/* Resource Alloc setting */
writel(0x48, regs_qos + QOS_RAS);
} else if (IS_ENABLED(CONFIG_R8A779H0) &&
renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779H0) {
/* Resource Alloc setting */
writel(0x30, regs_qos + QOS_RAS);
} else {
return -EINVAL;
}
writel(0x2020201, regs_qos + QOS_DANN_LOW);
writel(0x4040200, regs_qos + QOS_DANN_HIGH);
writel(0x181008, regs_qos + QOS_DANT);
writel(0x0, regs_qos + QOS_EMS_LOW);
writel(0x0, regs_qos + QOS_EMS_HIGH);
writel(0xA, regs_qos + QOS_FSS);
writel(0x30F0001, regs_qos + QOS_INSFC);
writel(0x0, regs_qos + QOS_EARLYR);
writel(0x50003, regs_qos + QOS_RACNT0);
writel(0x0, regs_qos + QOS_STATGEN0);
/* QoS MSTAT setting */
writel(0x70120, regs_qos + QOS_SL_INIT);
writel(0x11B0000, regs_qos + QOS_REF_ARS);
writel(0x12, regs_qos + QOS_REF_ENBL);
writel(0x4, regs_qos + QOS_BWG);
if (IS_ENABLED(CONFIG_R8A779G0) &&
renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779G0 &&
(renesas_get_cpu_rev_integer() < 2 ||
(renesas_get_cpu_rev_integer() == 2 &&
renesas_get_cpu_rev_fraction() <= 1))) {
/* OTLINT-5579: V4H <= rev2.1 DBSC W/A-3 */
writel(0x0, regs_axmm + AXMM_MMCR);
} else {
writel(0x10000, regs_axmm + AXMM_MMCR);
}
writel(0x3, ACTEXT_RT0_R);
writel(0x3, ACTEXT_RT0_W);
/*
* This may be necessary, but this IP is powered off at this point:
* writel(0x3, ACTEXT_IR0_R);
* writel(0x3, ACTEXT_IR0_W);
* writel(0x3, ACTEXT_IR1_R);
* writel(0x3, ACTEXT_IR1_W);
*/
if (IS_ENABLED(CONFIG_R8A779G0) &&
renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779G0) {
writel(0x10000, regs_axmm + AXMM_TR3CR);
if (renesas_get_cpu_rev_integer() >= 2) {
/* WA1 patch for IPL CA76 hang-up issue, REL_TRI_DN-7592 */
writel(0x38, SI0_RW_MAX);
writel(0x38, SI1_RW_MAX);
}
}
if (IS_ENABLED(CONFIG_R8A779H0) &&
renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779H0) {
writel(0x0, regs_axmm + AXMM_TR0CR0);
writel(0x0, regs_axmm + AXMM_TR1CR0);
writel(0x0, regs_axmm + AXMM_TR2CR0);
writel(0x0, regs_axmm + AXMM_TR3CR0);
writel(0x70707070, regs_axmm + AXMM_TR0CR1);
writel(0x70707070, regs_axmm + AXMM_TR1CR1);
writel(0x70707070, regs_axmm + AXMM_TR2CR1);
writel(0x70707070, regs_axmm + AXMM_TR3CR1);
writel(0x70707070, regs_axmm + AXMM_TR0CR2);
writel(0x70707070, regs_axmm + AXMM_TR1CR2);
writel(0x70707070, regs_axmm + AXMM_TR2CR2);
writel(0x70707070, regs_axmm + AXMM_TR3CR2);
}
for (i = 0U; i < ARRAY_SIZE(g_qosbw_tbl); i++) {
writeq(g_qosbw_tbl[i].fix, regs_qos + QOS_FIX_QOS_BANK0 + (i * 8));
writeq(g_qosbw_tbl[i].fix, regs_qos + QOS_FIX_QOS_BANK1 + (i * 8));
writeq(g_qosbw_tbl[i].be, regs_qos + QOS_BE_QOS_BANK0 + (i * 8));
writeq(g_qosbw_tbl[i].be, regs_qos + QOS_BE_QOS_BANK1 + (i * 8));
}
for (i = 0U; i < ARRAY_SIZE(g_qoswt_tbl); i++) {
writeq(g_qoswt_tbl[i].fix, regs_qos + QOSWT_FIX_QOS_BANK0 + (i * 8));
writeq(g_qoswt_tbl[i].fix, regs_qos + QOSWT_FIX_QOS_BANK1 + (i * 8));
writeq(g_qoswt_tbl[i].be, regs_qos + QOSWT_BE_QOS_BANK0 + (i * 8));
writeq(g_qoswt_tbl[i].be, regs_qos + QOSWT_BE_QOS_BANK1 + (i * 8));
}
/* QoS SRAM setting */
writel(0x1, regs_qos + QOS_RAEN);
writel(0x2080208, regs_qos + QOSWT_WTREF);
writel(0xD90050F, regs_qos + QOSWT_WTSET0);
writel(0xD90050F, regs_qos + QOSWT_WTSET1);
writel(0x1, regs_qos + QOSWT_WTEN);
writel(0x101, regs_qos + QOS_STATQC);
return 0;
}
static int renesas_dbsc5_qos_probe(struct udevice *dev)
{
int ret;
/* Setting the register of DBSC4 for QoS initialize */
ret = dbsc5_qos_dbsc_setting(dev);
if (ret)
return ret;
return dbsc5_qos_settings_init(dev);
}
static int renesas_dbsc5_qos_of_to_plat(struct udevice *dev)
{
struct renesas_dbsc5_qos_priv *priv = dev_get_priv(dev);
priv->regs = dev_read_addr_ptr(dev);
if (!priv->regs)
return -EINVAL;
return 0;
}
U_BOOT_DRIVER(renesas_dbsc5_qos) = {
.name = "dbsc5_qos",
.id = UCLASS_NOP,
.of_to_plat = renesas_dbsc5_qos_of_to_plat,
.probe = renesas_dbsc5_qos_probe,
.priv_auto = sizeof(struct renesas_dbsc5_qos_priv),
};

93
drivers/ram/renesas/dbsc5/rtvram.c Normal file
View File

@@ -0,0 +1,93 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2024 Renesas Electronics Corp.
*/
#include <asm/io.h>
#include <dm.h>
#include <errno.h>
#include <ram.h>
#include <linux/sizes.h>
/* RT-VRAM register base address */
#define RTVRAM_VBUF_CFG 0x6504
#define RTVRAM_VBUF_CFG_CACHE_MODE_8WAY (1 << 8)
#define RTVRAM_VBUF_CFG_VBUF_SIZE_28M (6 << 0)
#define RTVRAM_EXT_MODE 0x8500
#define RTVRAM_EXT_MODE_EXT BIT(0)
#define RTVRAM_VBUF_BADDR 0xC580
#define RTVRAM_VBUF_NUM 7
#define SDRAM_40BIT_ADDR_TOP 0x0400000000ULL
#define RTVRAM_VBUF_AREA_SIZE SZ_4M
struct renesas_dbsc5_rtvram_priv {
void __iomem *regs;
};
static int renesas_dbsc5_rtvram_probe(struct udevice *dev)
{
struct renesas_dbsc5_rtvram_priv *priv = dev_get_priv(dev);
u64 addr;
int i;
/* Set each 4MB from the top of SDRAM as the buffer area of RT-VRAM. */
for (i = 0; i < RTVRAM_VBUF_NUM; i++) {
addr = (SDRAM_40BIT_ADDR_TOP + (RTVRAM_VBUF_AREA_SIZE * i)) >> 16;
writel(lower_32_bits(addr), priv->regs + (RTVRAM_VBUF_BADDR + (4 * i)));
}
/* Cache Mode: 8-way, VBF size: 28M */
setbits_le32(priv->regs + RTVRAM_VBUF_CFG,
RTVRAM_VBUF_CFG_CACHE_MODE_8WAY | RTVRAM_VBUF_CFG_VBUF_SIZE_28M);
/* Change from Compatible Mode to Extended Mode */
writel(RTVRAM_EXT_MODE_EXT, priv->regs + RTVRAM_EXT_MODE);
dsb();
return 0;
}
static int renesas_dbsc5_rtvram_of_to_plat(struct udevice *dev)
{
struct renesas_dbsc5_rtvram_priv *priv = dev_get_priv(dev);
priv->regs = dev_read_addr_ptr(dev);
if (!priv->regs)
return -EINVAL;
return 0;
}
static int renesas_dbsc5_rtvram_get_info(struct udevice *dev,
struct ram_info *info)
{
struct renesas_dbsc5_rtvram_priv *priv = dev_get_priv(dev);
info->base = (phys_addr_t)priv->regs;
info->size = 28 * SZ_1M;
return 0;
}
static const struct ram_ops renesas_dbsc5_rtvram_ops = {
.get_info = renesas_dbsc5_rtvram_get_info,
};
static const struct udevice_id renesas_dbsc5_rtvram_ids[] = {
{ .compatible = "renesas,r8a779g0-rtvram" },
{ .compatible = "renesas,r8a779h0-rtvram" },
{ /* sentinel */ }
};
U_BOOT_DRIVER(renesas_dbsc5_rtvram) = {
.name = "rtvram",
.id = UCLASS_RAM,
.of_match = renesas_dbsc5_rtvram_ids,
.of_to_plat = renesas_dbsc5_rtvram_of_to_plat,
.ops = &renesas_dbsc5_rtvram_ops,
.probe = renesas_dbsc5_rtvram_probe,
.priv_auto = sizeof(struct renesas_dbsc5_rtvram_priv),
};