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rockchip: clk: pll: Fix constant typo

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Fixes: bbda2ed584 ("rockchip: clk: pll: add common pll setting funcs")
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Link: https://lore.kernel.org/r/20220928104129.13240-1-msuchanek@suse.de
This commit is contained in:
Michal Suchanek
2022-09-28 12:41:29 +02:00
committed by Sean Anderson
parent a1265cd580
commit aa36a74f0f
1 changed files with 3 additions and 3 deletions
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6
drivers/clk/rockchip/clk_pll.c
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@@ -31,7 +31,7 @@ static struct rockchip_pll_rate_table rockchip_auto_table;
#define RK3036_PLLCON1_DSMPD_SHIFT 12
#define RK3036_PLLCON2_FRAC_MASK 0xffffff
#define RK3036_PLLCON2_FRAC_SHIFT 0
#define RK3036_PLLCON1_PWRDOWN_SHIT 13
#define RK3036_PLLCON1_PWRDOWN_SHIFT 13
#define MHZ 1000000
#define KHZ 1000
@@ -207,7 +207,7 @@ static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll,
/* Power down */
rk_setreg(base + pll->con_offset + 0x4,
1 << RK3036_PLLCON1_PWRDOWN_SHIT);
1 << RK3036_PLLCON1_PWRDOWN_SHIFT);
rk_clrsetreg(base + pll->con_offset,
(RK3036_PLLCON0_POSTDIV1_MASK |
@@ -231,7 +231,7 @@ static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll,
/* Power Up */
rk_clrreg(base + pll->con_offset + 0x4,
1 << RK3036_PLLCON1_PWRDOWN_SHIT);
1 << RK3036_PLLCON1_PWRDOWN_SHIFT);
/* waiting for pll lock */
while (!(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift)))