board: arbel: Limit the dram effective size to bank0 maximal size
For 4GB dram size, the dram is divided into 2 banks and the address space of these 2 banks are not concatenated. Limit the gd->ram_top to not exceed bank0 top to prevent accessing invalid memory region. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
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@@ -27,6 +27,15 @@ int board_init(void)
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return 0;
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}
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phys_size_t get_effective_memsize(void)
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{
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/* Use bank0 only */
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if (gd->ram_size > DRAM_2GB_SIZE)
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return DRAM_2GB_SIZE;
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return gd->ram_size;
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}
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int dram_init(void)
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{
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struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
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@@ -70,21 +79,16 @@ int dram_init_banksize(void)
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gd->bd->bi_dram[1].start = DRAM_4GB_SIZE;
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gd->bd->bi_dram[1].size = DRAM_2GB_SIZE -
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(DRAM_4GB_SIZE - DRAM_4GB_ECC_SIZE);
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/* use bank0 only */
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gd->ram_size = DRAM_2GB_SIZE;
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break;
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case DRAM_4GB_SIZE:
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gd->bd->bi_dram[0].size = DRAM_2GB_SIZE;
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gd->bd->bi_dram[1].start = DRAM_4GB_SIZE;
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gd->bd->bi_dram[1].size = DRAM_2GB_SIZE;
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/* use bank0 only */
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gd->ram_size = DRAM_2GB_SIZE;
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break;
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default:
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gd->bd->bi_dram[0].size = DRAM_1GB_SIZE;
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gd->bd->bi_dram[1].start = 0;
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gd->bd->bi_dram[1].size = 0;
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gd->ram_size = DRAM_1GB_SIZE;
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break;
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}
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