board: arbel: Limit the dram effective size to bank0 maximal size

For 4GB dram size, the dram is divided into 2 banks and
the address space of these 2 banks are not concatenated.
Limit the gd->ram_top to not exceed bank0 top to prevent
accessing invalid memory region.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
This commit is contained in:
Jim Liu
2024-04-23 15:22:10 +08:00
committed by Tom Rini
parent e7c3948ec5
commit b3c0b94f2e

View File

@@ -27,6 +27,15 @@ int board_init(void)
return 0;
}
phys_size_t get_effective_memsize(void)
{
/* Use bank0 only */
if (gd->ram_size > DRAM_2GB_SIZE)
return DRAM_2GB_SIZE;
return gd->ram_size;
}
int dram_init(void)
{
struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
@@ -70,21 +79,16 @@ int dram_init_banksize(void)
gd->bd->bi_dram[1].start = DRAM_4GB_SIZE;
gd->bd->bi_dram[1].size = DRAM_2GB_SIZE -
(DRAM_4GB_SIZE - DRAM_4GB_ECC_SIZE);
/* use bank0 only */
gd->ram_size = DRAM_2GB_SIZE;
break;
case DRAM_4GB_SIZE:
gd->bd->bi_dram[0].size = DRAM_2GB_SIZE;
gd->bd->bi_dram[1].start = DRAM_4GB_SIZE;
gd->bd->bi_dram[1].size = DRAM_2GB_SIZE;
/* use bank0 only */
gd->ram_size = DRAM_2GB_SIZE;
break;
default:
gd->bd->bi_dram[0].size = DRAM_1GB_SIZE;
gd->bd->bi_dram[1].start = 0;
gd->bd->bi_dram[1].size = 0;
gd->ram_size = DRAM_1GB_SIZE;
break;
}