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riscv: don't read riscv, isa in the riscv cpu's get_desc()

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cpu_get_desc() for the RISC-V CPU currently reads "riscv,isa" to get
the description, but it is no longer a required property and cannot be
assummed to always be present, as the new "riscv,isa-extensions" and
"riscv,isa-base" properties may be present instead.

On RISC-V, cpu_get_desc() has two main uses - firstly providing an
informational name for the CPU for smbios or at boot with
DISPLAY_CPUINFO etc and secondly it forms the basis of ISA extension
detection in supports_extension() as it returns (a portion of) an ISA
string.

cpu_get_desc() returns a string, which aligned with "riscv,isa" but
the new property is a list of strings. Rather than add support for
the list of strings property, which would require creating an isa
string from "riscv,isa-extensions", modify the RISC-V CPU's
implementaion of cpu_get_desc() return the first compatible as the
cpu description instead. This may be fine for the informational cases,
but it would break extension dtection, given supports_extension()
expects cpu_get_desc() to return an ISA string.

Call dev_read_string() directly in supports_extension() to get the
contents of "riscv,isa" so that extension detection remains functional.
As a knock-on affect of this change, extension detection is no longer
broken for long ISA strings. Previously if the ISA string exceeded the
32 element array that supports_extension() passed to cpu_get_desc(),
it would return ENOSPC and no extensions would be detected.
This bug probably had no impact as U-Boot does not currently do anything
meaningful with the results of supports_extension() and most SoCs
supported by U-Boot don't have anywhere near that complex of an ISA
string. The QEMU virt machine's CPUs do however, so extension detection
doesn't work there.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This commit is contained in:
Conor Dooley
2024-03-18 15:16:02 +00:00
committed by Leo Yu-Chi Liang
parent 3a95532ac7
commit b90edde701
2 changed files with 11 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
arch/riscv/cpu/cpu.c
View File

@@ -39,7 +39,7 @@ static inline bool supports_extension(char ext)
return csr_read(CSR_MISA) & (1 << (ext - 'a'));
#elif CONFIG_CPU
struct udevice *dev;
char desc[32];
const char *isa;
int i;
uclass_find_first_device(UCLASS_CPU, &dev);
@@ -47,12 +47,14 @@ static inline bool supports_extension(char ext)
debug("unable to find the RISC-V cpu device\n");
return false;
}
if (!cpu_get_desc(dev, desc, sizeof(desc))) {
isa = dev_read_string(dev, "riscv,isa");
if (isa) {
/*
* skip the first 4 characters (rv32|rv64)
*/
for (i = 4; i < sizeof(desc); i++) {
switch (desc[i]) {
for (i = 4; i < sizeof(isa); i++) {
switch (isa[i]) {
case 's':
case 'x':
case 'z':
@@ -64,7 +66,7 @@ static inline bool supports_extension(char ext)
*/
return false;
default:
if (desc[i] == ext)
if (isa[i] == ext)
return true;
}
}

8
drivers/cpu/riscv_cpu.c
View File

@@ -21,13 +21,13 @@ DECLARE_GLOBAL_DATA_PTR;
static int riscv_cpu_get_desc(const struct udevice *dev, char *buf, int size)
{
const char *isa;
const char *cpu;
isa = dev_read_string(dev, "riscv,isa");
if (size < (strlen(isa) + 1))
cpu = dev_read_string(dev, "compatible");
if (size < (strlen(cpu) + 1))
return -ENOSPC;
strcpy(buf, isa);
strcpy(buf, cpu);
return 0;
}