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Merge patch series "powerpc: Fix and enforce distinction between immediates and registers"

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J. Neuschäfer <j.ne@posteo.net> says:

This patchset changes the definition r0 etc. to %r0, so that the
assembler can check that registers are only used where expected, and
fixes the fallout.

Link: https://lore.kernel.org/r/20241212-gpr-checks-v1-0-8c084c5fc0b6@posteo.net
This commit is contained in:
Tom Rini
2024-12-30 15:55:11 -06:00
parent 787d389350 c3e425ead4
commit c379590ab7
5 changed files with 85 additions and 85 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/powerpc/config.mk
View File

@@ -8,7 +8,7 @@ LDFLAGS_FINAL += --bss-plt
PLATFORM_RELFLAGS += -fpic -mrelocatable -ffunction-sections \
-fdata-sections -mcall-linux
PF_CPPFLAGS_POWERPC := $(call cc-option,-fno-ira-hoist-pressure,)
PF_CPPFLAGS_POWERPC := $(call cc-option,-fno-ira-hoist-pressure,) $(call cc-option,-Xassembler --fatal-warnings,)
PLATFORM_CPPFLAGS += -D__powerpc__ -ffixed-r2 -m32 $(PF_CPPFLAGS_POWERPC)
KBUILD_LDFLAGS += -m32 -melf32ppclinux

72
arch/powerpc/cpu/mpc83xx/start.S
View File

@@ -550,133 +550,133 @@ init_e300_core: /* time t 10 */
/* setup_bats - set them up to some initial state */
.globl setup_bats
setup_bats:
addis r0, r0, 0x0000
addis r0, 0, 0x0000
/* IBAT 0 */
addis r4, r0, CFG_SYS_IBAT0L@h
addis r4, 0, CFG_SYS_IBAT0L@h
ori r4, r4, CFG_SYS_IBAT0L@l
addis r3, r0, CFG_SYS_IBAT0U@h
addis r3, 0, CFG_SYS_IBAT0U@h
ori r3, r3, CFG_SYS_IBAT0U@l
mtspr IBAT0L, r4
mtspr IBAT0U, r3
/* DBAT 0 */
addis r4, r0, CFG_SYS_DBAT0L@h
addis r4, 0, CFG_SYS_DBAT0L@h
ori r4, r4, CFG_SYS_DBAT0L@l
addis r3, r0, CFG_SYS_DBAT0U@h
addis r3, 0, CFG_SYS_DBAT0U@h
ori r3, r3, CFG_SYS_DBAT0U@l
mtspr DBAT0L, r4
mtspr DBAT0U, r3
/* IBAT 1 */
addis r4, r0, CFG_SYS_IBAT1L@h
addis r4, 0, CFG_SYS_IBAT1L@h
ori r4, r4, CFG_SYS_IBAT1L@l
addis r3, r0, CFG_SYS_IBAT1U@h
addis r3, 0, CFG_SYS_IBAT1U@h
ori r3, r3, CFG_SYS_IBAT1U@l
mtspr IBAT1L, r4
mtspr IBAT1U, r3
/* DBAT 1 */
addis r4, r0, CFG_SYS_DBAT1L@h
addis r4, 0, CFG_SYS_DBAT1L@h
ori r4, r4, CFG_SYS_DBAT1L@l
addis r3, r0, CFG_SYS_DBAT1U@h
addis r3, 0, CFG_SYS_DBAT1U@h
ori r3, r3, CFG_SYS_DBAT1U@l
mtspr DBAT1L, r4
mtspr DBAT1U, r3
/* IBAT 2 */
addis r4, r0, CFG_SYS_IBAT2L@h
addis r4, 0, CFG_SYS_IBAT2L@h
ori r4, r4, CFG_SYS_IBAT2L@l
addis r3, r0, CFG_SYS_IBAT2U@h
addis r3, 0, CFG_SYS_IBAT2U@h
ori r3, r3, CFG_SYS_IBAT2U@l
mtspr IBAT2L, r4
mtspr IBAT2U, r3
/* DBAT 2 */
addis r4, r0, CFG_SYS_DBAT2L@h
addis r4, 0, CFG_SYS_DBAT2L@h
ori r4, r4, CFG_SYS_DBAT2L@l
addis r3, r0, CFG_SYS_DBAT2U@h
addis r3, 0, CFG_SYS_DBAT2U@h
ori r3, r3, CFG_SYS_DBAT2U@l
mtspr DBAT2L, r4
mtspr DBAT2U, r3
/* IBAT 3 */
addis r4, r0, CFG_SYS_IBAT3L@h
addis r4, 0, CFG_SYS_IBAT3L@h
ori r4, r4, CFG_SYS_IBAT3L@l
addis r3, r0, CFG_SYS_IBAT3U@h
addis r3, 0, CFG_SYS_IBAT3U@h
ori r3, r3, CFG_SYS_IBAT3U@l
mtspr IBAT3L, r4
mtspr IBAT3U, r3
/* DBAT 3 */
addis r4, r0, CFG_SYS_DBAT3L@h
addis r4, 0, CFG_SYS_DBAT3L@h
ori r4, r4, CFG_SYS_DBAT3L@l
addis r3, r0, CFG_SYS_DBAT3U@h
addis r3, 0, CFG_SYS_DBAT3U@h
ori r3, r3, CFG_SYS_DBAT3U@l
mtspr DBAT3L, r4
mtspr DBAT3U, r3
#ifdef CONFIG_HIGH_BATS
/* IBAT 4 */
addis r4, r0, CFG_SYS_IBAT4L@h
addis r4, 0, CFG_SYS_IBAT4L@h
ori r4, r4, CFG_SYS_IBAT4L@l
addis r3, r0, CFG_SYS_IBAT4U@h
addis r3, 0, CFG_SYS_IBAT4U@h
ori r3, r3, CFG_SYS_IBAT4U@l
mtspr IBAT4L, r4
mtspr IBAT4U, r3
/* DBAT 4 */
addis r4, r0, CFG_SYS_DBAT4L@h
addis r4, 0, CFG_SYS_DBAT4L@h
ori r4, r4, CFG_SYS_DBAT4L@l
addis r3, r0, CFG_SYS_DBAT4U@h
addis r3, 0, CFG_SYS_DBAT4U@h
ori r3, r3, CFG_SYS_DBAT4U@l
mtspr DBAT4L, r4
mtspr DBAT4U, r3
/* IBAT 5 */
addis r4, r0, CFG_SYS_IBAT5L@h
addis r4, 0, CFG_SYS_IBAT5L@h
ori r4, r4, CFG_SYS_IBAT5L@l
addis r3, r0, CFG_SYS_IBAT5U@h
addis r3, 0, CFG_SYS_IBAT5U@h
ori r3, r3, CFG_SYS_IBAT5U@l
mtspr IBAT5L, r4
mtspr IBAT5U, r3
/* DBAT 5 */
addis r4, r0, CFG_SYS_DBAT5L@h
addis r4, 0, CFG_SYS_DBAT5L@h
ori r4, r4, CFG_SYS_DBAT5L@l
addis r3, r0, CFG_SYS_DBAT5U@h
addis r3, 0, CFG_SYS_DBAT5U@h
ori r3, r3, CFG_SYS_DBAT5U@l
mtspr DBAT5L, r4
mtspr DBAT5U, r3
/* IBAT 6 */
addis r4, r0, CFG_SYS_IBAT6L@h
addis r4, 0, CFG_SYS_IBAT6L@h
ori r4, r4, CFG_SYS_IBAT6L@l
addis r3, r0, CFG_SYS_IBAT6U@h
addis r3, 0, CFG_SYS_IBAT6U@h
ori r3, r3, CFG_SYS_IBAT6U@l
mtspr IBAT6L, r4
mtspr IBAT6U, r3
/* DBAT 6 */
addis r4, r0, CFG_SYS_DBAT6L@h
addis r4, 0, CFG_SYS_DBAT6L@h
ori r4, r4, CFG_SYS_DBAT6L@l
addis r3, r0, CFG_SYS_DBAT6U@h
addis r3, 0, CFG_SYS_DBAT6U@h
ori r3, r3, CFG_SYS_DBAT6U@l
mtspr DBAT6L, r4
mtspr DBAT6U, r3
/* IBAT 7 */
addis r4, r0, CFG_SYS_IBAT7L@h
addis r4, 0, CFG_SYS_IBAT7L@h
ori r4, r4, CFG_SYS_IBAT7L@l
addis r3, r0, CFG_SYS_IBAT7U@h
addis r3, 0, CFG_SYS_IBAT7U@h
ori r3, r3, CFG_SYS_IBAT7U@l
mtspr IBAT7L, r4
mtspr IBAT7U, r3
/* DBAT 7 */
addis r4, r0, CFG_SYS_DBAT7L@h
addis r4, 0, CFG_SYS_DBAT7L@h
ori r4, r4, CFG_SYS_DBAT7L@l
addis r3, r0, CFG_SYS_DBAT7U@h
addis r3, 0, CFG_SYS_DBAT7U@h
ori r3, r3, CFG_SYS_DBAT7U@l
mtspr DBAT7L, r4
mtspr DBAT7U, r3
@@ -1057,7 +1057,7 @@ lock_ram_in_cache:
(CFG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
mtctr r4
1:
dcbz r0, r3
dcbz 0, r3
addi r3, r3, 32
bdnz 1b
@@ -1078,8 +1078,8 @@ unlock_ram_in_cache:
li r4, ((CFG_SYS_INIT_RAM_SIZE & ~31) + \
(CFG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
mtctr r4
1: icbi r0, r3
dcbi r0, r3
1: icbi 0, r3
dcbi 0, r3
addi r3, r3, 32
bdnz 1b
sync /* Wait for all icbi to complete on bus */

24
arch/powerpc/cpu/mpc85xx/start.S
View File

@@ -1203,12 +1203,12 @@ switch_as:
mtctr r2
li r0,0
1:
dcbz r0,r3
dcbz 0,r3
#ifdef CONFIG_E6500 /* Lock/unlock L2 cache long with L1 */
dcbtls 2, r0, r3
dcbtls 0, r0, r3
dcbtls 2, 0, r3
dcbtls 0, 0, r3
#else
dcbtls 0, r0, r3
dcbtls 0, 0, r3
#endif
addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
bdnz 1b
@@ -1514,7 +1514,7 @@ out16:
/*------------------------------------------------------------------------------- */
.globl out16r
out16r:
sthbrx r4,r0,r3
sthbrx r4,0,r3
sync
blr
@@ -1534,7 +1534,7 @@ out32:
/*------------------------------------------------------------------------------- */
.globl out32r
out32r:
stwbrx r4,r0,r3
stwbrx r4,0,r3
sync
blr
@@ -1553,7 +1553,7 @@ in16:
/*------------------------------------------------------------------------------- */
.globl in16r
in16r:
lhbrx r3,r0,r3
lhbrx r3,0,r3
blr
/*------------------------------------------------------------------------------- */
@@ -1571,7 +1571,7 @@ in32:
/*------------------------------------------------------------------------------- */
.globl in32r
in32r:
lwbrx r3,r0,r3
lwbrx r3,0,r3
blr
#endif /* !MINIMAL_SPL */
@@ -1832,12 +1832,12 @@ unlock_ram_in_cache:
andi. r4,r4,0x1ff
slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
mtctr r4
1: dcbi r0,r3
1: dcbi 0,r3
#ifdef CONFIG_E6500 /* lock/unlock L2 cache long with L1 */
dcblc 2, r0, r3
dcblc 0, r0, r3
dcblc 2, 0, r3
dcblc 0, 0, r3
#else
dcblc r0,r3
dcblc 0,r3
#endif
addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
bdnz 1b

6
arch/powerpc/lib/ppccache.S
View File

@@ -20,7 +20,7 @@
/*------------------------------------------------------------------------------- */
.globl ppcDcbf
ppcDcbf:
dcbf r0,r3
dcbf 0,r3
blr
/*------------------------------------------------------------------------------- */
@@ -31,7 +31,7 @@ ppcDcbf:
/*------------------------------------------------------------------------------- */
.globl ppcDcbi
ppcDcbi:
dcbi r0,r3
dcbi 0,r3
blr
/*--------------------------------------------------------------------------
@@ -43,7 +43,7 @@ ppcDcbi:
.globl ppcDcbz
ppcDcbz:
dcbz r0,r3
dcbz 0,r3
blr
/*------------------------------------------------------------------------------- */

66
include/ppc_asm.tmpl
View File

@@ -45,40 +45,40 @@
/***************************************************************************
* Register names
* Register names. The %r1 offers some error-checking in GNU as.
*/
#define r0 0
#define r1 1
#define r2 2
#define r3 3
#define r4 4
#define r5 5
#define r6 6
#define r7 7
#define r8 8
#define r9 9
#define r10 10
#define r11 11
#define r12 12
#define r13 13
#define r14 14
#define r15 15
#define r16 16
#define r17 17
#define r18 18
#define r19 19
#define r20 20
#define r21 21
#define r22 22
#define r23 23
#define r24 24
#define r25 25
#define r26 26
#define r27 27
#define r28 28
#define r29 29
#define r30 30
#define r31 31
#define r0 %r0
#define r1 %r1
#define r2 %r2
#define r3 %r3
#define r4 %r4
#define r5 %r5
#define r6 %r6
#define r7 %r7
#define r8 %r8
#define r9 %r9
#define r10 %r10
#define r11 %r11
#define r12 %r12
#define r13 %r13
#define r14 %r14
#define r15 %r15
#define r16 %r16
#define r17 %r17
#define r18 %r18
#define r19 %r19
#define r20 %r20
#define r21 %r21
#define r22 %r22
#define r23 %r23
#define r24 %r24
#define r25 %r25
#define r26 %r26
#define r27 %r27
#define r28 %r28
#define r29 %r29
#define r30 %r30
#define r31 %r31
#if defined(CONFIG_MPC8xx)