pickman: Record cherry-pick of 9 commits from us/next

- 6e18eec908 ARM: dts: imx: Make DRAM coding GPIOs available before relocation on Data Modul i.MX8M Mini/Plus eDM SBC
- 1171adfd89 ARM: dts: imx: Pick safe DRAM size on failure on Data Modul i.MX8M Mini/Plus eDM SBC
- ec3e5fa55d ARM: imx: Perform plain boot in altbootcmd on Data Modul i.MX8M Mini/Plus eDM SBC
- 3a689038bf ARM: imx: Deduplicate Data Modul i.MX8M eDM SBC defconfigs
- 0b97a394f6 ARM: imx: Replace YModem with SDP on Data Modul i.MX8M Mini eDM SBC SPL
- 4835efca7a ARM: dts: imx: Enable PCIe and NVMe on Data Modul i.MX8M Mini eDM SBC
- 6ceb861882 Revert "arm64: dts: ti: k3-j7200: Fix OSPI boot"
- 20f641987f test/cmd/wget.c: move net_test_wget() to the cmd test suite
- bf3dfb405b Merge tag 'u-boot-imx-master-20241130' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

.pickman-history

@@ -232,3 +232,142 @@ The branch `cherry-06b8aafd681` was created based on `ci/master` but is identica
 
 ---
 
+## 2025-12-16: us/next
+
+Branch: cherry-91bc909d317
+
+Commits:
+- 91bc909d317 spl: increase SPL_SYS_MALLOC_SIZE when using BIOSEMU on RISC-V
+- afc52da8946 configs: SiFive Unmatched: enable 'env erase' sub-command
+- 185986caebf configs: visionfive2: re-enable SPL_SYS_MMCSD_RAW_MODE
+- bdca70632da configs: enable CONFIG_PCI_REGION_MULTI_ENTRY=y in sifive_unmatched_defconfig
+- b51b97e9be1 Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
+
+### Conversation log
+The repository state is clean. Now let me create and checkout a new branch based on ci/master:
+
+Now let me cherry-pick each commit in order. Let me start with the first commit:
+
+There's a conflict. Let me examine it:
+
+I can see the conflict. The HEAD has a more general `RISCV` condition with a larger size (0x800000), while the commit being cherry-picked adds a more specific `BIOSEMU && RISCV` condition with 0x180000. Since HEAD already has a larger allocation for RISCV, the incoming change is redundant. Let me resolve this by keeping the HEAD version since it already provides sufficient malloc size for RISCV:
+
+The commit became empty because the HEAD already has a better solution. Let me skip this commit and move to the next one:
+
+Now let me cherry-pick the second commit:
+
+Second commit applied successfully. Now the third commit:
+
+This commit is also already applied. Let me skip it:
+
+Now the fourth commit:
+
+Fourth commit applied. Now the fifth commit which is a merge commit:
+
+There's a conflict. Let me examine it:
+
+Same conflict as before - HEAD already has the larger allocation for RISCV. Let me resolve by keeping the HEAD version:
+
+This merge commit also became empty. Let me skip it:
+
+Now let me verify the results with git log:
+
+I see that only 2 commits were applied (the other 3 were already present in ci/master or resolved to empty). Now let me run the build verification:
+
+The build succeeded. Let me provide a summary:
+
+## Final Status
+
+### Cherry-Pick Results
+
+| Commit | Description | Result |
+|--------|-------------|--------|
+| 91bc909d317 | spl: increase SPL_SYS_MALLOC_SIZE when using BIOSEMU on RISC-V | **Skipped** - Already applied (ci/master has `0x800000 if RISCV` which supersedes this) |
+| afc52da8946 | configs: SiFive Unmatched: enable 'env erase' sub-command | **Applied** ✓ |
+| 185986caebf | configs: visionfive2: re-enable SPL_SYS_MMCSD_RAW_MODE | **Skipped** - Already applied |
+| bdca70632da | configs: enable CONFIG_PCI_REGION_MULTI_ENTRY=y in sifive_unmatched_defconfig | **Applied** ✓ |
+| b51b97e9be1 | Merge https://source.denx.de/u-boot/custodians/u-boot-riscv | **Skipped** - Already applied (merge commit content already in ci/master) |
+
+### Build Result
+- **Status:** ✅ OK
+- **Board:** sandbox
+- **Output:** `/tmp/pickman`
+
+### Fix-ups Made
+- None required - conflicts were resolved by keeping the existing HEAD versions which already contained the equivalent or better changes.
+
+### Branch Status
+- Branch `cherry-91bc909d317` is ready for pushing
+- 2 new commits ahead of `ci/master`
+- 3 commits were skipped (already present in ci/master)
+
+---
+
+## 2025-12-16: us/next
+
+Branch: cherry-6e18eec9080
+
+Commits:
+- 6e18eec9080 ARM: dts: imx: Make DRAM coding GPIOs available before relocation on Data Modul i.MX8M Mini/Plus eDM SBC
+- 1171adfd899 ARM: dts: imx: Pick safe DRAM size on failure on Data Modul i.MX8M Mini/Plus eDM SBC
+- ec3e5fa55d8 ARM: imx: Perform plain boot in altbootcmd on Data Modul i.MX8M Mini/Plus eDM SBC
+- 3a689038bf9 ARM: imx: Deduplicate Data Modul i.MX8M eDM SBC defconfigs
+- 0b97a394f6b ARM: imx: Replace YModem with SDP on Data Modul i.MX8M Mini eDM SBC SPL
+- 4835efca7a0 ARM: dts: imx: Enable PCIe and NVMe on Data Modul i.MX8M Mini eDM SBC
+- 6ceb861882b Revert "arm64: dts: ti: k3-j7200: Fix OSPI boot"
+- 20f641987f8 test/cmd/wget.c: move net_test_wget() to the cmd test suite
+- bf3dfb405ba Merge tag 'u-boot-imx-master-20241130' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
+
+### Conversation log
+The repository is clean. Now let me create and checkout a new branch based on ci/master:
+
+Now let me cherry-pick each commit in order. I'll start with the first commit:
+
+There are conflicts. Let me check the conflicting files:
+
+Let me also check the other file:
+
+I can see the conflict. The commit is trying to deduplicate the defconfigs by moving common settings into a shared include file. The conflict shows that the main content should be removed (keeping only the #include and the platform-specific settings). Let me check what the original commit looks like:
+
+Now I understand the conflict. The original commit removes all the common settings and moves them to the shared config file, but the base branch has slightly different content. The resolution should keep the "theirs" version (the incoming commit's version). Let me resolve by using the incoming commit's version:
+
+Let me now amend this commit to note the conflict resolution:
+
+Now let me continue with the next cherry-pick:
+
+Now the last one is the merge commit - I'll use -m 1 --allow-empty:
+
+All cherry-picks are complete. Let me verify with git log:
+
+All 9 commits are present. Now let me run the build verification:
+
+The build completed successfully with no warnings or errors.
+
+## Final Status Summary
+
+### Cherry-pick Results
+All 9 commits have been successfully cherry-picked from `us/next` branch to `cherry-6e18eec9080`:
+
+| # | Commit | Subject | Status |
+|---|--------|---------|--------|
+| 1 | 6e18eec9080 | ARM: dts: imx: Make DRAM coding GPIOs available before relocation | ✅ Clean |
+| 2 | 1171adfd899 | ARM: dts: imx: Pick safe DRAM size on failure | ✅ Clean |
+| 3 | ec3e5fa55d8 | ARM: imx: Perform plain boot in altbootcmd | ✅ Clean |
+| 4 | 3a689038bf9 | ARM: imx: Deduplicate Data Modul i.MX8M eDM SBC defconfigs | ⚠️ Conflict resolved |
+| 5 | 0b97a394f6b | ARM: imx: Replace YModem with SDP on Data Modul i.MX8M Mini eDM SBC SPL | ✅ Clean |
+| 6 | 4835efca7a0 | ARM: dts: imx: Enable PCIe and NVMe on Data Modul i.MX8M Mini eDM SBC | ✅ Clean |
+| 7 | 6ceb861882b | Revert "arm64: dts: ti: k3-j7200: Fix OSPI boot" | ✅ Clean |
+| 8 | 20f641987f8 | test/cmd/wget.c: move net_test_wget() to the cmd test suite | ✅ Clean (auto-merged) |
+| 9 | bf3dfb405ba | Merge tag 'u-boot-imx-master-20241130' | ✅ Empty (expected) |
+
+### Build Result
+**✅ OK** - Sandbox build completed successfully with no warnings or errors.
+
+### Fix-ups Made
+- **Commit 3a689038bf9**: Resolved merge conflicts in `configs/imx8mm_data_modul_edm_sbc_defconfig` and `configs/imx8mp_data_modul_edm_sbc_defconfig` by accepting the incoming commit version. This was the correct resolution since the commit deduplicates defconfigs by moving common settings to a shared include file.
+
+### Current Branch State
+Branch `cherry-6e18eec9080` is ready for pushing and is ahead of `ci/master` by 9 commits.
+
+---
+

arch/arm/dts/bcm47622.dtsi

@@ -1,126 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 Broadcom Ltd.
- */
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
-	compatible = "brcm,bcm47622", "brcm,bcmbca";
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	interrupt-parent = <&gic>;
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		CA7_0: cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x0>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		CA7_1: cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x1>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-		CA7_2: cpu@2 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x2>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-		CA7_3: cpu@3 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x3>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-		L2_0: l2-cache0 {
-			compatible = "cache";
-		};
-	};
-
-	timer {
-		compatible = "arm,armv7-timer";
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
-		arm,cpu-registers-not-fw-configured;
-	};
-
-	pmu: pmu {
-		compatible = "arm,cortex-a7-pmu";
-		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&CA7_0>, <&CA7_1>,
-			<&CA7_2>, <&CA7_3>;
-	};
-
-	clocks: clocks {
-		periph_clk: periph-clk {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <200000000>;
-		};
-		uart_clk: uart-clk {
-			compatible = "fixed-factor-clock";
-			#clock-cells = <0>;
-			clocks = <&periph_clk>;
-			clock-div = <4>;
-			clock-mult = <1>;
-		};
-	};
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-		cpu_off = <1>;
-		cpu_on = <2>;
-	};
-
-	axi@81000000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0x81000000 0x818000>;
-
-		gic: interrupt-controller@1000 {
-			compatible = "arm,cortex-a7-gic";
-			#interrupt-cells = <3>;
-			#address-cells = <0>;
-			interrupt-controller;
-			reg = <0x1000 0x1000>,
-				<0x2000 0x2000>;
-		};
-	};
-
-	bus@ff800000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0xff800000 0x800000>;
-
-		uart0: serial@12000 {
-			compatible = "arm,pl011", "arm,primecell";
-			reg = <0x12000 0x1000>;
-			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&uart_clk>, <&uart_clk>;
-			clock-names = "uartclk", "apb_pclk";
-			status = "disabled";
-		};
-	};
-};

arch/arm/dts/bcm4912.dtsi

@@ -1,128 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 Broadcom Ltd.
- */
-
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-/ {
-	compatible = "brcm,bcm4912", "brcm,bcmbca";
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	interrupt-parent = <&gic>;
-
-	cpus {
-		#address-cells = <2>;
-		#size-cells = <0>;
-
-		B53_0: cpu@0 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x0>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		B53_1: cpu@1 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x1>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		B53_2: cpu@2 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x2>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		B53_3: cpu@3 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x3>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		L2_0: l2-cache0 {
-			compatible = "cache";
-		};
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
-	};
-
-	pmu: pmu {
-		compatible = "arm,cortex-a53-pmu";
-		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&B53_0>, <&B53_1>,
-			<&B53_2>, <&B53_3>;
-	};
-
-	clocks: clocks {
-		periph_clk: periph-clk {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <200000000>;
-		};
-		uart_clk: uart-clk {
-			compatible = "fixed-factor-clock";
-			#clock-cells = <0>;
-			clocks = <&periph_clk>;
-			clock-div = <4>;
-			clock-mult = <1>;
-		};
-	};
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	axi@81000000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x0 0x0 0x81000000 0x8000>;
-
-		gic: interrupt-controller@1000 {
-			compatible = "arm,gic-400";
-			#interrupt-cells = <3>;
-			interrupt-controller;
-			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-			reg = <0x1000 0x1000>,
-				<0x2000 0x2000>,
-				<0x4000 0x2000>,
-				<0x6000 0x2000>;
-		};
-	};
-
-	bus@ff800000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x0 0x0 0xff800000 0x800000>;
-
-		uart0: serial@12000 {
-			compatible = "arm,pl011", "arm,primecell";
-			reg = <0x12000 0x1000>;
-			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&uart_clk>, <&uart_clk>;
-			clock-names = "uartclk", "apb_pclk";
-			status = "disabled";
-		};
-	};
-};

arch/arm/dts/bcm63146.dtsi

@@ -1,110 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 Broadcom Ltd.
- */
-
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-/ {
-	compatible = "brcm,bcm63146", "brcm,bcmbca";
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	interrupt-parent = <&gic>;
-
-	cpus {
-		#address-cells = <2>;
-		#size-cells = <0>;
-
-		B53_0: cpu@0 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x0>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		B53_1: cpu@1 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x1>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		L2_0: l2-cache0 {
-			compatible = "cache";
-		};
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
-	};
-
-	pmu: pmu {
-		compatible = "arm,cortex-a53-pmu";
-		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&B53_0>, <&B53_1>;
-	};
-
-	clocks: clocks {
-		periph_clk: periph-clk {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <200000000>;
-		};
-		uart_clk: uart-clk {
-			compatible = "fixed-factor-clock";
-			#clock-cells = <0>;
-			clocks = <&periph_clk>;
-			clock-div = <4>;
-			clock-mult = <1>;
-		};
-	};
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	axi@81000000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x0 0x0 0x81000000 0x8000>;
-
-		gic: interrupt-controller@1000 {
-			compatible = "arm,gic-400";
-			#interrupt-cells = <3>;
-			interrupt-controller;
-			reg = <0x1000 0x1000>,
-				<0x2000 0x2000>,
-				<0x4000 0x2000>,
-				<0x6000 0x2000>;
-			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
-					IRQ_TYPE_LEVEL_HIGH)>;
-		};
-	};
-
-	bus@ff800000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x0 0x0 0xff800000 0x800000>;
-
-		uart0: serial@12000 {
-			compatible = "arm,pl011", "arm,primecell";
-			reg = <0x12000 0x1000>;
-			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&uart_clk>, <&uart_clk>;
-			clock-names = "uartclk", "apb_pclk";
-			status = "disabled";
-		};
-	};
-};

arch/arm/dts/bcm63158.dtsi

@@ -1,278 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com>
- * Copyright 2022 Broadcom Ltd.
- */
-
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-/ {
-	compatible = "brcm,bcm63158", "brcm,bcmbca";
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	interrupt-parent = <&gic>;
-
-	cpus {
-		#address-cells = <2>;
-		#size-cells = <0>;
-
-		B53_0: cpu@0 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x0>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		B53_1: cpu@1 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x1>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		B53_2: cpu@2 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x2>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		B53_3: cpu@3 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x3>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		L2_0: l2-cache0 {
-			compatible = "cache";
-		};
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
-	};
-
-	pmu: pmu {
-		compatible = "arm,cortex-a53-pmu";
-		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&B53_0>, <&B53_1>,
-			<&B53_2>, <&B53_3>;
-	};
-
-	clocks {
-		bootph-all;
-		periph_clk: periph-clk {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <200000000>;
-		};
-
-		hsspi_pll: hsspi-pll {
-			compatible = "fixed-factor-clock";
-			#clock-cells = <0>;
-			clocks = <&periph_clk>;
-			clock-mult = <2>;
-			clock-div = <1>;
-		};
-
-		uart_clk: uart-clk {
-			compatible = "fixed-factor-clock";
-			#clock-cells = <0>;
-			clocks = <&periph_clk>;
-			clock-div = <4>;
-			clock-mult = <1>;
-		};
-
-		wdt_clk: wdt-clk {
-			compatible = "fixed-factor-clock";
-			#clock-cells = <0>;
-			clocks = <&periph_clk>;
-			clock-div = <4>;
-			clock-mult = <1>;
-		};
-	};
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	axi@81000000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x0 0x0 0x81000000 0x8000>;
-
-		gic: interrupt-controller@1000 {
-			compatible = "arm,gic-400";
-			#interrupt-cells = <3>;
-			interrupt-controller;
-			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-			reg = <0x1000 0x1000>,
-				<0x2000 0x2000>,
-				<0x4000 0x2000>,
-				<0x6000 0x2000>;
-		};
-	};
-
-	bus@ff800000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x0 0x0 0xff800000 0x800000>;
-		bootph-all;
-
-		uart0: serial@12000 {
-			compatible = "arm,pl011", "arm,primecell";
-			reg = <0x12000 0x1000>;
-			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&uart_clk>, <&uart_clk>;
-			clock-names = "uartclk", "apb_pclk";
-			status = "disabled";
-		};
-
-		leds: led-controller@800 {
-			compatible = "brcm,bcm6858-leds";
-			reg = <0x800 0xe4>;
-
-			status = "disabled";
-		};
-
-		wdt1: watchdog@480 {
-			compatible = "brcm,bcm6345-wdt";
-			reg = <0x480 0x14>;
-			clocks = <&wdt_clk>;
-		};
-
-		wdt2: watchdog@4c0 {
-			compatible = "brcm,bcm6345-wdt";
-			reg = <0x4c0 0x14>;
-			clocks = <&wdt_clk>;
-		};
-
-		wdt-reboot {
-			compatible = "wdt-reboot";
-			wdt = <&wdt1>;
-		};
-
-		gpio0: gpio-controller@500 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x500 0x4>,
-			      <0x520 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio1: gpio-controller@504 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x504 0x4>,
-			      <0x524 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio2: gpio-controller@508 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x508 0x4>,
-			      <0x528 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio3: gpio-controller@50c {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x50c 0x4>,
-			      <0x52c 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio4: gpio-controller@510 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x510 0x4>,
-			      <0x530 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio5: gpio-controller@514 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x514 0x4>,
-			      <0x534 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio6: gpio-controller@518 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x518 0x4>,
-			      <0x538 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio7: gpio-controller@51c {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x51c 0x4>,
-			      <0x53c 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		hsspi: spi-controller@1000 {
-			compatible = "brcm,bcm6328-hsspi";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x1000 0x600>;
-			clocks = <&hsspi_pll>, <&hsspi_pll>;
-			clock-names = "hsspi", "pll";
-			spi-max-frequency = <100000000>;
-			num-cs = <8>;
-
-			status = "disabled";
-		};
-
-		nand: nand-controller@1800 {
-			compatible = "brcm,nand-bcm63158",
-				     "brcm,brcmnand-v5.0",
-				     "brcm,brcmnand";
-			reg-names = "nand", "nand-int-base", "nand-cache";
-			reg = <0x1800 0x180>,
-			      <0x2000 0x10>,
-			      <0x1c00 0x200>;
-			parameter-page-big-endian = <0>;
-
-			status = "disabled";
-		};
-	};
-};

arch/arm/dts/bcm63178.dtsi

@@ -1,120 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 Broadcom Ltd.
- */
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
-	compatible = "brcm,bcm63178", "brcm,bcmbca";
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	interrupt-parent = <&gic>;
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		CA7_0: cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x0>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		CA7_1: cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x1>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		CA7_2: cpu@2 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x2>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		L2_0: l2-cache0 {
-			compatible = "cache";
-		};
-	};
-
-	timer {
-		compatible = "arm,armv7-timer";
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>;
-		arm,cpu-registers-not-fw-configured;
-	};
-
-	pmu: pmu {
-		compatible = "arm,cortex-a7-pmu";
-		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&CA7_0>, <&CA7_1>,
-			<&CA7_2>;
-	};
-
-	clocks: clocks {
-		periph_clk: periph-clk {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <200000000>;
-		};
-		uart_clk: uart-clk {
-			compatible = "fixed-factor-clock";
-			#clock-cells = <0>;
-			clocks = <&periph_clk>;
-			clock-div = <4>;
-			clock-mult = <1>;
-		};
-	};
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	axi@81000000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0x81000000 0x8000>;
-
-		gic: interrupt-controller@1000 {
-			compatible = "arm,cortex-a7-gic";
-			#interrupt-cells = <3>;
-			interrupt-controller;
-			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>;
-			reg = <0x1000 0x1000>,
-				<0x2000 0x2000>,
-				<0x4000 0x2000>,
-				<0x6000 0x2000>;
-		};
-	};
-
-	bus@ff800000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0xff800000 0x800000>;
-
-		uart0: serial@12000 {
-			compatible = "arm,pl011", "arm,primecell";
-			reg = <0x12000 0x1000>;
-			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&uart_clk>, <&uart_clk>;
-			clock-names = "uartclk", "apb_pclk";
-			status = "disabled";
-		};
-	};
-};

arch/arm/dts/bcm6756.dtsi

@@ -1,130 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 Broadcom Ltd.
- */
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
-	compatible = "brcm,bcm6756", "brcm,bcmbca";
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	interrupt-parent = <&gic>;
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		CA7_0: cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x0>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		CA7_1: cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x1>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		CA7_2: cpu@2 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x2>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		CA7_3: cpu@3 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x3>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		L2_0: l2-cache0 {
-			compatible = "cache";
-		};
-	};
-
-	timer {
-		compatible = "arm,armv7-timer";
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
-		arm,cpu-registers-not-fw-configured;
-	};
-
-	pmu: pmu {
-		compatible = "arm,cortex-a7-pmu";
-		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&CA7_0>, <&CA7_1>,
-			<&CA7_2>, <&CA7_3>;
-	};
-
-	clocks: clocks {
-		periph_clk: periph-clk {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <200000000>;
-		};
-
-		uart_clk: uart-clk {
-			compatible = "fixed-factor-clock";
-			#clock-cells = <0>;
-			clocks = <&periph_clk>;
-			clock-div = <4>;
-			clock-mult = <1>;
-		};
-	};
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	axi@81000000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0x81000000 0x8000>;
-
-		gic: interrupt-controller@1000 {
-			compatible = "arm,cortex-a7-gic";
-			#interrupt-cells = <3>;
-			interrupt-controller;
-			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-			reg = <0x1000 0x1000>,
-				<0x2000 0x2000>,
-				<0x4000 0x2000>,
-				<0x6000 0x2000>;
-		};
-	};
-
-	bus@ff800000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0xff800000 0x800000>;
-
-		uart0: serial@12000 {
-			compatible = "arm,pl011", "arm,primecell";
-			reg = <0x12000 0x1000>;
-			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&uart_clk>, <&uart_clk>;
-			clock-names = "uartclk", "apb_pclk";
-			status = "disabled";
-		};
-	};
-};

arch/arm/dts/bcm6813.dtsi

@@ -1,128 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 Broadcom Ltd.
- */
-
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-/ {
-	compatible = "brcm,bcm6813", "brcm,bcmbca";
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	interrupt-parent = <&gic>;
-
-	cpus {
-		#address-cells = <2>;
-		#size-cells = <0>;
-
-		B53_0: cpu@0 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x0>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		B53_1: cpu@1 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x1>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		B53_2: cpu@2 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x2>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		B53_3: cpu@3 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x3>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		L2_0: l2-cache0 {
-			compatible = "cache";
-		};
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
-	};
-
-	pmu: pmu {
-		compatible = "arm,cortex-a53-pmu";
-		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&B53_0>, <&B53_1>,
-			<&B53_2>, <&B53_3>;
-	};
-
-	clocks: clocks {
-		periph_clk: periph-clk {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <200000000>;
-		};
-		uart_clk: uart-clk {
-			compatible = "fixed-factor-clock";
-			#clock-cells = <0>;
-			clocks = <&periph_clk>;
-			clock-div = <4>;
-			clock-mult = <1>;
-		};
-	};
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	axi@81000000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x0 0x0 0x81000000 0x8000>;
-
-		gic: interrupt-controller@1000 {
-			compatible = "arm,gic-400";
-			#interrupt-cells = <3>;
-			interrupt-controller;
-			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-			reg = <0x1000 0x1000>,
-				<0x2000 0x2000>,
-				<0x4000 0x2000>,
-				<0x6000 0x2000>;
-		};
-	};
-
-	bus@ff800000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x0 0x0 0xff800000 0x800000>;
-
-		uart0: serial@12000 {
-			compatible = "arm,pl011", "arm,primecell";
-			reg = <0x12000 0x1000>;
-			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&uart_clk>, <&uart_clk>;
-			clock-names = "uartclk", "apb_pclk";
-			status = "disabled";
-		};
-	};
-};

arch/arm/dts/bcm6855.dtsi

@@ -1,257 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2022 Philippe Reynes <philippe.reynes@softathome.com>
- * Copyright 2022 Broadcom Ltd.
- */
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
-	compatible = "brcm,bcm6855", "brcm,bcmbca";
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	interrupt-parent = <&gic>;
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		CA7_0: cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x0>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		CA7_1: cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x1>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		CA7_2: cpu@2 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x2>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		L2_0: l2-cache0 {
-			compatible = "cache";
-		};
-	};
-
-	timer {
-		compatible = "arm,armv7-timer";
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>;
-		arm,cpu-registers-not-fw-configured;
-	};
-
-	pmu: pmu {
-		compatible = "arm,cortex-a7-pmu";
-		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&CA7_0>, <&CA7_1>, <&CA7_2>;
-	};
-
-	clocks: clocks {
-		bootph-all;
-
-		periph_clk: periph-clk {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <200000000>;
-		};
-
-		uart_clk: uart-clk {
-			compatible = "fixed-factor-clock";
-			#clock-cells = <0>;
-			clocks = <&periph_clk>;
-			clock-div = <4>;
-			clock-mult = <1>;
-		};
-
-		hsspi_pll: hsspi-pll {
-			compatible = "fixed-factor-clock";
-			#clock-cells = <0>;
-			clocks = <&periph_clk>;
-			clock-mult = <2>;
-			clock-div = <1>;
-		};
-
-		wdt_clk: wdt-clk {
-			compatible = "fixed-factor-clock";
-			#clock-cells = <0>;
-			clocks = <&periph_clk>;
-			clock-div = <4>;
-			clock-mult = <1>;
-		};
-	};
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	axi@81000000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0x81000000 0x8000>;
-
-		gic: interrupt-controller@1000 {
-			compatible = "arm,cortex-a7-gic";
-			#interrupt-cells = <3>;
-			interrupt-controller;
-			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>;
-			reg = <0x1000 0x1000>,
-				<0x2000 0x2000>,
-				<0x4000 0x2000>,
-				<0x6000 0x2000>;
-		};
-	};
-
-	bus@ff800000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0xff800000 0x800000>;
-		bootph-all;
-
-		uart0: serial@12000 {
-			compatible = "arm,pl011", "arm,primecell";
-			reg = <0x12000 0x1000>;
-			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&uart_clk>, <&uart_clk>;
-			clock-names = "uartclk", "apb_pclk";
-			status = "disabled";
-		};
-
-		wdt1: watchdog@480 {
-			compatible = "brcm,bcm6345-wdt";
-			reg = <0x480 0x14>;
-			clocks = <&wdt_clk>;
-		};
-
-		wdt2: watchdog@4c0 {
-			compatible = "brcm,bcm6345-wdt";
-			reg = <0x4c0 0x14>;
-			clocks = <&wdt_clk>;
-		};
-
-		wdt-reboot {
-			compatible = "wdt-reboot";
-			wdt = <&wdt1>;
-		};
-
-		gpio0: gpio-controller@500 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x500 0x4>,
-			      <0x520 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio1: gpio-controller@504 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x504 0x4>,
-			      <0x524 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio2: gpio-controller@508 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x508 0x4>,
-			      <0x528 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio3: gpio-controller@50c {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x50c 0x4>,
-			      <0x52c 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio4: gpio-controller@510 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x510 0x4>,
-			      <0x530 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio5: gpio-controller@514 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x514 0x4>,
-			      <0x534 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio6: gpio-controller@518 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x518 0x4>,
-			      <0x538 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio7: gpio-controller@51c {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x51c 0x4>,
-			      <0x53c 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		nand: nand-controller@1800 {
-			compatible = "brcm,nand-bcm6753",
-				     "brcm,brcmnand-v5.0",
-				     "brcm,brcmnand";
-			reg-names = "nand", "nand-int-base", "nand-cache";
-			reg = <0x1800 0x180>,
-			      <0x2000 0x10>,
-			      <0x1c00 0x200>;
-			parameter-page-big-endian = <0>;
-
-			status = "disabled";
-		};
-
-		leds: led-controller@3000 {
-			compatible = "brcm,bcm6753-leds";
-			reg = <0x3000 0x3480>;
-
-			status = "disabled";
-		};
-	};
-};

arch/arm/dts/bcm6856.dtsi

@@ -1,253 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2020 Philippe Reynes <philippe.reynes@softathome.com>
- * Copyright 2022 Broadcom Ltd.
- */
-
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-/ {
-	compatible = "brcm,bcm6856", "brcm,bcmbca";
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	interrupt-parent = <&gic>;
-
-	cpus {
-		#address-cells = <2>;
-		#size-cells = <0>;
-
-		B53_0: cpu@0 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x0>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		B53_1: cpu@1 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x1>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		L2_0: l2-cache0 {
-			compatible = "cache";
-		};
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
-	};
-
-	pmu: pmu {
-		compatible = "arm,cortex-a53-pmu";
-		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&B53_0>, <&B53_1>;
-	};
-
-	clocks: clocks {
-		bootph-all;
-
-		periph_clk:periph-clk {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <200000000>;
-		};
-
-		hsspi_pll: hsspi-pll {
-			compatible = "fixed-factor-clock";
-			#clock-cells = <0>;
-			clocks = <&periph_clk>;
-			clock-mult = <2>;
-			clock-div = <1>;
-		};
-
-		wdt_clk: wdt-clk {
-			compatible = "fixed-factor-clock";
-			#clock-cells = <0>;
-			clocks = <&periph_clk>;
-			clock-div = <4>;
-			clock-mult = <1>;
-		};
-	};
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	axi@81000000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x0 0x0 0x81000000 0x8000>;
-
-		gic: interrupt-controller@1000 {
-			compatible = "arm,gic-400";
-			#interrupt-cells = <3>;
-			interrupt-controller;
-			reg = <0x1000 0x1000>, /* GICD */
-				<0x2000 0x2000>, /* GICC */
-				<0x4000 0x2000>, /* GICH */
-				<0x6000 0x2000>; /* GICV */
-			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
-					IRQ_TYPE_LEVEL_HIGH)>;
-		};
-	};
-
-	bus@ff800000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x0 0x0 0xff800000 0x800000>;
-		bootph-all;
-
-		uart0: serial@640 {
-			compatible = "brcm,bcm6345-uart";
-			reg = <0x640 0x18>;
-			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&periph_clk>;
-			clock-names = "refclk";
-			status = "disabled";
-		};
-
-		wdt1: watchdog@480 {
-			compatible = "brcm,bcm6345-wdt";
-			reg = <0x480 0x14>;
-			clocks = <&wdt_clk>;
-		};
-
-		wdt2: watchdog@4c0 {
-			compatible = "brcm,bcm6345-wdt";
-			reg = <0x4c0 0x14>;
-			clocks = <&wdt_clk>;
-		};
-
-		wdt-reboot {
-			compatible = "wdt-reboot";
-			wdt = <&wdt1>;
-		};
-
-		leds: led-controller@800 {
-			compatible = "brcm,bcm6858-leds";
-			reg = <0x800 0xe4>;
-
-			status = "disabled";
-		};
-
-		gpio0: gpio-controller@500 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x500 0x4>,
-			      <0x520 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio1: gpio-controller@504 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x504 0x4>,
-			      <0x524 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio2: gpio-controller@508 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x508 0x4>,
-			      <0x528 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio3: gpio-controller@50c {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x50c 0x4>,
-			      <0x52c 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio4: gpio-controller@510 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x510 0x4>,
-			      <0x530 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio5: gpio-controller@514 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x514 0x4>,
-			      <0x534 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio6: gpio-controller@518 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x518 0x4>,
-			      <0x538 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio7: gpio-controller@51c {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x51c 0x4>,
-			      <0x53c 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		hsspi: spi-controller@1000 {
-			compatible = "brcm,bcm6328-hsspi";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x1000 0x600>;
-			clocks = <&hsspi_pll>, <&hsspi_pll>;
-			clock-names = "hsspi", "pll";
-			spi-max-frequency = <100000000>;
-			num-cs = <8>;
-
-			status = "disabled";
-		};
-
-		nand: nand-controller@1800 {
-			compatible = "brcm,nand-bcm68360",
-				     "brcm,brcmnand-v5.0",
-				     "brcm,brcmnand";
-			reg-names = "nand", "nand-int-base", "nand-cache";
-			reg = <0x1800 0x180>,
-			      <0x2000 0x10>,
-			      <0x1c00 0x200>;
-			parameter-page-big-endian = <0>;
-
-			status = "disabled";
-		};
-	};
-};

arch/arm/dts/bcm6858.dtsi

@@ -1,272 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
- * Copyright 2022 Broadcom Ltd.
- */
-
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-/ {
-	compatible = "brcm,bcm6858", "brcm,bcmbca";
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	interrupt-parent = <&gic>;
-
-	cpus {
-		#address-cells = <2>;
-		#size-cells = <0>;
-
-		B53_0: cpu@0 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x0>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		B53_1: cpu@1 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x1>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		B53_2: cpu@2 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x2>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		B53_3: cpu@3 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x3>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		L2_0: l2-cache0 {
-			compatible = "cache";
-		};
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
-	};
-
-	pmu: pmu {
-		compatible = "arm,armv8-pmuv3";
-		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&B53_0>, <&B53_1>,
-			<&B53_2>, <&B53_3>;
-	};
-
-	clocks {
-		bootph-all;
-
-		periph_clk: periph_clk {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <200000000>;
-		};
-
-		hsspi_pll: hsspi-pll {
-			compatible = "fixed-factor-clock";
-			#clock-cells = <0>;
-			clocks = <&periph_clk>;
-			clock-mult = <2>;
-			clock-div = <1>;
-		};
-
-		wdt_clk: wdt-clk {
-			compatible = "fixed-factor-clock";
-			#clock-cells = <0>;
-			clocks = <&periph_clk>;
-			clock-div = <4>;
-			clock-mult = <1>;
-		};
-	};
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	axi@81000000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x0 0x0 0x81000000 0x8000>;
-
-		gic: interrupt-controller@1000 {
-			compatible = "arm,gic-400";
-			#interrupt-cells = <3>;
-			interrupt-controller;
-			reg = <0x1000 0x1000>, /* GICD */
-				<0x2000 0x2000>, /* GICC */
-				<0x4000 0x2000>, /* GICH */
-				<0x6000 0x2000>; /* GICV */
-			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
-					IRQ_TYPE_LEVEL_HIGH)>;
-		};
-	};
-
-	bus@ff800000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x0 0x0 0xff800000 0x800000>;
-		bootph-all;
-
-		uart0: serial@640 {
-			compatible = "brcm,bcm6345-uart";
-			reg = <0x640 0x18>;
-			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&periph_clk>;
-			clock-names = "refclk";
-			status = "disabled";
-		};
-
-		leds: led-controller@800 {
-			compatible = "brcm,bcm6858-leds";
-			reg = <0x800 0xe4>;
-
-			status = "disabled";
-		};
-
-		wdt1: watchdog@2780 {
-			compatible = "brcm,bcm6345-wdt";
-			reg = <0x2780 0x14>;
-			clocks = <&wdt_clk>;
-		};
-
-		wdt2: watchdog@27c0 {
-			compatible = "brcm,bcm6345-wdt";
-			reg = <0x27c0 0x14>;
-			clocks = <&wdt_clk>;
-		};
-
-		wdt-reboot {
-			compatible = "wdt-reboot";
-			wdt = <&wdt1>;
-		};
-
-		gpio0: gpio-controller@500 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x500 0x4>,
-			      <0x520 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio1: gpio-controller@504 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x504 0x4>,
-			      <0x524 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio2: gpio-controller@508 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x508 0x4>,
-			      <0x528 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio3: gpio-controller@50c {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x50c 0x4>,
-			      <0x52c 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio4: gpio-controller@510 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x510 0x4>,
-			      <0x530 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio5: gpio-controller@514 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x514 0x4>,
-			      <0x534 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio6: gpio-controller@518 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x518 0x4>,
-			      <0x538 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio7: gpio-controller@51c {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x51c 0x4>,
-			      <0x53c 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		hsspi: spi-controller@1000 {
-			compatible = "brcm,bcm6328-hsspi";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x1000 0x600>;
-			clocks = <&hsspi_pll>, <&hsspi_pll>;
-			clock-names = "hsspi", "pll";
-			spi-max-frequency = <100000000>;
-			num-cs = <8>;
-
-			status = "disabled";
-		};
-
-		nand: nand-controller@1800 {
-			compatible = "brcm,nand-bcm6858",
-				     "brcm,brcmnand-v5.0",
-				     "brcm,brcmnand";
-			reg-names = "nand", "nand-int-base", "nand-cache";
-			reg = <0x1800 0x180>,
-			      <0x2000 0x10>,
-			      <0x1c00 0x200>;
-			parameter-page-big-endian = <0>;
-
-			status = "disabled";
-		};
-	};
-};

arch/arm/dts/bcm6878.dtsi

@@ -1,111 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 Broadcom Ltd.
- */
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
-	compatible = "brcm,bcm6878", "brcm,bcmbca";
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	interrupt-parent = <&gic>;
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		CA7_0: cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x0>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		CA7_1: cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x1>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		L2_0: l2-cache0 {
-			compatible = "cache";
-		};
-	};
-
-	timer {
-		compatible = "arm,armv7-timer";
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
-		arm,cpu-registers-not-fw-configured;
-	};
-
-	pmu: pmu {
-		compatible = "arm,cortex-a7-pmu";
-		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&CA7_0>, <&CA7_1>;
-	};
-
-	clocks: clocks {
-		periph_clk: periph-clk {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <200000000>;
-		};
-		uart_clk: uart-clk {
-			compatible = "fixed-factor-clock";
-			#clock-cells = <0>;
-			clocks = <&periph_clk>;
-			clock-div = <4>;
-			clock-mult = <1>;
-		};
-	};
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	axi@81000000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0x81000000 0x8000>;
-
-		gic: interrupt-controller@1000 {
-			compatible = "arm,cortex-a7-gic";
-			#interrupt-cells = <3>;
-			interrupt-controller;
-			reg = <0x1000 0x1000>,
-				<0x2000 0x2000>,
-				<0x4000 0x2000>,
-				<0x6000 0x2000>;
-			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
-					IRQ_TYPE_LEVEL_HIGH)>;
-		};
-	};
-
-	bus@ff800000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0xff800000 0x800000>;
-
-		uart0: serial@12000 {
-			compatible = "arm,pl011", "arm,primecell";
-			reg = <0x12000 0x1000>;
-			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&uart_clk>, <&uart_clk>;
-			clock-names = "uartclk", "apb_pclk";
-			status = "disabled";
-		};
-	};
-};

arch/arm/dts/bcm947622.dts

@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2019 Broadcom Ltd.
- */
-
-/dts-v1/;
-
-#include "bcm47622.dtsi"
-
-/ {
-	model = "Broadcom BCM947622 Reference Board";
-	compatible = "brcm,bcm947622", "brcm,bcm47622", "brcm,bcmbca";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x08000000>;
-	};
-};
-
-&uart0 {
-	status = "okay";
-};

arch/arm/dts/bcm94912.dts

@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 Broadcom Ltd.
- */
-
-/dts-v1/;
-
-#include "bcm4912.dtsi"
-
-/ {
-	model = "Broadcom BCM94912 Reference Board";
-	compatible = "brcm,bcm94912", "brcm,bcm4912", "brcm,bcmbca";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x0 0x0 0x08000000>;
-	};
-};
-
-&uart0 {
-	status = "okay";
-};

arch/arm/dts/bcm963146.dts

@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 Broadcom Ltd.
- */
-
-/dts-v1/;
-
-#include "bcm63146.dtsi"
-
-/ {
-	model = "Broadcom BCM963146 Reference Board";
-	compatible = "brcm,bcm963146", "brcm,bcm63146", "brcm,bcmbca";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x0 0x0 0x08000000>;
-	};
-};
-
-&uart0 {
-	status = "okay";
-};

arch/arm/dts/bcm963158.dts

@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 Broadcom Ltd.
- */
-
-/dts-v1/;
-
-#include "bcm63158.dtsi"
-
-/ {
-	model = "Broadcom BCM963158 Reference Board";
-	compatible = "brcm,bcm963158", "brcm,bcm63158", "brcm,bcmbca";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x0 0x0 0x08000000>;
-	};
-};
-
-&uart0 {
-	status = "okay";
-};

arch/arm/dts/bcm963178.dts

@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2019 Broadcom Ltd.
- */
-
-/dts-v1/;
-
-#include "bcm63178.dtsi"
-
-/ {
-	model = "Broadcom BCM963178 Reference Board";
-	compatible = "brcm,bcm963178", "brcm,bcm63178", "brcm,bcmbca";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x08000000>;
-	};
-};
-
-&uart0 {
-	status = "okay";
-};

arch/arm/dts/bcm96756.dts

@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2019 Broadcom Ltd.
- */
-
-/dts-v1/;
-
-#include "bcm6756.dtsi"
-
-/ {
-	model = "Broadcom BCM96756 Reference Board";
-	compatible = "brcm,bcm96756", "brcm,bcm6756", "brcm,bcmbca";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x08000000>;
-	};
-};
-
-&uart0 {
-	status = "okay";
-};

arch/arm/dts/bcm96813.dts

@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 Broadcom Ltd.
- */
-
-/dts-v1/;
-
-#include "bcm6813.dtsi"
-
-/ {
-	model = "Broadcom BCM96813 Reference Board";
-	compatible = "brcm,bcm96813", "brcm,bcm6813", "brcm,bcmbca";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x0 0x0 0x08000000>;
-	};
-};
-
-&uart0 {
-	status = "okay";
-};

arch/arm/dts/bcm96855.dts

@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 Broadcom Ltd.
- */
-
-/dts-v1/;
-
-#include "bcm6855.dtsi"
-
-/ {
-	model = "Broadcom BCM96855 Reference Board";
-	compatible = "brcm,bcm96855", "brcm,bcm6855", "brcm,bcmbca";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x08000000>;
-	};
-};
-
-&uart0 {
-	status = "okay";
-};

arch/arm/dts/bcm96856.dts

@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 Broadcom Ltd.
- */
-
-/dts-v1/;
-
-#include "bcm6856.dtsi"
-
-/ {
-	model = "Broadcom BCM96856 Reference Board";
-	compatible = "brcm,bcm96856", "brcm,bcm6856", "brcm,bcmbca";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x0 0x0 0x08000000>;
-	};
-};
-
-&uart0 {
-	status = "okay";
-};

arch/arm/dts/bcm96858.dts

@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 Broadcom Ltd.
- */
-
-/dts-v1/;
-
-#include "bcm6858.dtsi"
-
-/ {
-	model = "Broadcom BCM96858 Reference Board";
-	compatible = "brcm,bcm96858", "brcm,bcm6858", "brcm,bcmbca";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x0 0x0 0x08000000>;
-	};
-};
-
-&uart0 {
-	status = "okay";
-};

arch/arm/dts/bcm96878.dts

@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2019 Broadcom Ltd.
- */
-
-/dts-v1/;
-
-#include "bcm6878.dtsi"
-
-/ {
-	model = "Broadcom BCM96878 Reference Board";
-	compatible = "brcm,bcm96878", "brcm,bcm6878", "brcm,bcmbca";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x08000000>;
-	};
-};
-
-&uart0 {
-	status = "okay";
-};

arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi

@@ -16,6 +16,12 @@
 		dmo,ram-coding-gpios = <&gpio2 8 0>, <&gpio2 1 0>, <&gpio2 0 0>;
 	};
 
+	clk_pcie100: clk-pcie100 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+
 	wdt-reboot {
 		compatible = "wdt-reboot";
 		wdt = <&wdog1>;
@@ -35,6 +41,15 @@
 	bootph-pre-ram;
 };
 
+&pcie_phy {
+	clocks = <&clk_pcie100>;
+};
+
+&pcie0 {
+	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
+		 <&clk_pcie100>;
+};
+
 &pinctrl_hog_sbc {
 	bootph-pre-ram;
 };
@@ -77,6 +92,7 @@
 
 &gpio2 {
 	bootph-pre-ram;
+	bootph-some-ram;
 
 	dsi-reset-hog {
 		bootph-pre-ram;
@@ -144,8 +160,17 @@
 	bootph-pre-ram;
 };
 
+&usbmisc1 {
+	bootph-pre-ram;
+};
+
+&usbphynop1 {
+	bootph-pre-ram;
+};
+
 &usbotg1 {
 	dr_mode = "peripheral";
+	bootph-pre-ram;
 };
 
 &usdhc2 {

arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi

@@ -64,6 +64,7 @@
 
 &gpio3 {
 	bootph-pre-ram;
+	bootph-some-ram;
 
 	bl-enable-hog {
 		bootph-pre-ram;
@@ -92,6 +93,7 @@
 
 &gpio4 {
 	bootph-pre-ram;
+	bootph-some-ram;
 
 	dsi-reset-hog {
 		bootph-pre-ram;

arch/arm/mach-bcmbca/bcm47622/Kconfig

@@ -8,6 +8,7 @@ if BCM47622
 config TARGET_BCM947622
 	bool "Broadcom 47622 Reference Board"
 	depends on ARCH_BCMBCA
+	imply OF_UPSTREAM
 
 config SYS_SOC
 	default "bcm47622"

arch/arm/mach-bcmbca/bcm4912/Kconfig

@@ -8,6 +8,7 @@ if BCM4912
 config TARGET_BCM94912
 	bool "Broadcom 4912 Reference Board"
 	depends on ARCH_BCMBCA
+	imply OF_UPSTREAM
 
 config SYS_SOC
 	default "bcm4912"

arch/arm/mach-bcmbca/bcm63146/Kconfig

@@ -8,6 +8,7 @@ if BCM63146
 config TARGET_BCM963146
 	bool "Broadcom 63146 Reference Board"
 	depends on ARCH_BCMBCA
+	imply OF_UPSTREAM
 
 config SYS_SOC
 	default "bcm63146"

arch/arm/mach-bcmbca/bcm63158/Kconfig

@@ -8,6 +8,7 @@ if BCM63158
 config TARGET_BCM963158
 	bool "Broadcom 63158 Reference Board"
 	depends on ARCH_BCMBCA
+	imply OF_UPSTREAM
 
 config SYS_SOC
 	default "bcm63158"

arch/arm/mach-bcmbca/bcm63178/Kconfig

@@ -8,6 +8,7 @@ if BCM63178
 config TARGET_BCM963178
 	bool "Broadcom 63178 Reference Board"
 	depends on ARCH_BCMBCA
+	imply OF_UPSTREAM
 
 config SYS_SOC
 	default "bcm63178"

arch/arm/mach-bcmbca/bcm6756/Kconfig

@@ -8,6 +8,7 @@ if BCM6756
 config TARGET_BCM96756
 	bool "Broadcom 6756 Reference Board"
 	depends on ARCH_BCMBCA
+	imply OF_UPSTREAM
 
 config SYS_SOC
 	default "bcm6756"

arch/arm/mach-bcmbca/bcm6813/Kconfig

@@ -8,6 +8,7 @@ if BCM6813
 config TARGET_BCM96813
 	bool "Broadcom 6813 Reference Board"
 	depends on ARCH_BCMBCA
+	imply OF_UPSTREAM
 
 config SYS_SOC
 	default "bcm6813"

arch/arm/mach-bcmbca/bcm6855/Kconfig

@@ -8,6 +8,7 @@ if BCM6855
 config TARGET_BCM96855
 	bool "Broadcom 6855 Reference Board"
 	depends on ARCH_BCMBCA
+	imply OF_UPSTREAM
 
 config SYS_SOC
 	default "bcm6855"

arch/arm/mach-bcmbca/bcm6856/Kconfig

@@ -8,6 +8,7 @@ if BCM6856
 config TARGET_BCM96856
 	bool "Broadcom 6856 Reference Board"
 	depends on ARCH_BCMBCA
+	imply OF_UPSTREAM
 
 config SYS_SOC
 	default "bcm6856"

arch/arm/mach-bcmbca/bcm6858/Kconfig

@@ -8,6 +8,7 @@ if BCM6858
 config TARGET_BCM96858
 	bool "Broadcom 6858 Reference Board"
 	depends on ARCH_BCMBCA
+	imply OF_UPSTREAM
 
 config SYS_SOC
 	default "bcm6858"

arch/arm/mach-bcmbca/bcm6878/Kconfig

@@ -8,6 +8,7 @@ if BCM6878
 config TARGET_BCM96878
 	bool "Broadcom 6878 Reference Board"
 	depends on ARCH_BCMBCA
+	imply OF_UPSTREAM
 
 config SYS_SOC
 	default "bcm6878"

board/data_modul/common/common.c

@@ -47,6 +47,9 @@ u8 dmo_get_memcfg(void)
 					      "dmo,ram-coding-gpios",
 					      gpio, ARRAY_SIZE(gpio),
 					      GPIOD_IS_IN);
+	if (ret < 0)
+		return BIT(2) | BIT(0);
+
 	for (i = 0; i < ret; i++)
 		memcfg |= !!dm_gpio_get_value(&(gpio[i])) << i;
 

board/data_modul/imx8mm_edm_sbc/spl.c

@@ -61,8 +61,10 @@ int spl_board_boot_device(enum boot_device boot_dev_spl)
 {
 	if (boot_dev_spl == MMC3_BOOT)
 		return BOOT_DEVICE_MMC2;	/* eMMC */
-	else
+	else if (boot_dev_spl == MMC2_BOOT)
 		return BOOT_DEVICE_MMC1;	/* SD */
+	else
+		return BOOT_DEVICE_BOARD;
 }
 
 void board_boot_order(u32 *spl_boot_list)
@@ -76,7 +78,7 @@ void board_boot_order(u32 *spl_boot_list)
 	else
 		spl_boot_list[1] = BOOT_DEVICE_MMC1;	/* SD */
 
-	spl_boot_list[2] = BOOT_DEVICE_UART;	/* YModem */
+	spl_boot_list[2] = BOOT_DEVICE_BOARD;	/* SDP */
 	spl_boot_list[3] = BOOT_DEVICE_NONE;
 }
 

configs/bcm947622_defconfig

@@ -8,7 +8,7 @@ CONFIG_TARGET_BCM947622=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
-CONFIG_DEFAULT_DEVICE_TREE="bcm947622"
+CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcm947622"
 CONFIG_SYS_BOOTM_LEN=0x2000000
 CONFIG_SYS_LOAD_ADDR=0x01000000
 CONFIG_IDENT_STRING=" Broadcom BCM47622"
@@ -16,6 +16,15 @@ CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_NAND=y
 CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
 CONFIG_OF_EMBED=y
+CONFIG_DM=y
 CONFIG_CLK=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_NAND_BRCMNAND_BCMBCA=y

configs/bcm94912_defconfig

@@ -9,13 +9,22 @@ CONFIG_TARGET_BCM94912=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
-CONFIG_DEFAULT_DEVICE_TREE="bcm94912"
+CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcmbca/bcm94912"
 CONFIG_SYS_LOAD_ADDR=0x01000000
 CONFIG_IDENT_STRING=" Broadcom BCM4912"
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_NAND=y
 CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
 CONFIG_OF_EMBED=y
+CONFIG_DM=y
 CONFIG_CLK=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_NAND_BRCMNAND_BCMBCA=y

configs/bcm963146_defconfig

@@ -9,13 +9,22 @@ CONFIG_TARGET_BCM963146=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
-CONFIG_DEFAULT_DEVICE_TREE="bcm963146"
+CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcmbca/bcm963146"
 CONFIG_SYS_LOAD_ADDR=0x01000000
 CONFIG_IDENT_STRING=" Broadcom BCM63146"
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_NAND=y
 CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
 CONFIG_OF_EMBED=y
+CONFIG_DM=y
 CONFIG_CLK=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_NAND_BRCMNAND_BCMBCA=y

configs/bcm963158_defconfig

@@ -9,13 +9,22 @@ CONFIG_TARGET_BCM963158=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
-CONFIG_DEFAULT_DEVICE_TREE="bcm963158"
+CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcmbca/bcm963158"
 CONFIG_SYS_LOAD_ADDR=0x01000000
 CONFIG_IDENT_STRING=" Broadcom BCM63158"
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_NAND=y
 CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
 CONFIG_OF_EMBED=y
+CONFIG_DM=y
 CONFIG_CLK=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_NAND_BRCMNAND_BCMBCA=y

configs/bcm963178_defconfig

@@ -9,7 +9,7 @@ CONFIG_TARGET_BCM963178=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
-CONFIG_DEFAULT_DEVICE_TREE="bcm963178"
+CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcm963178"
 CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_SYS_LOAD_ADDR=0x01000000
 CONFIG_IDENT_STRING=" Broadcom BCM63178"
@@ -17,6 +17,15 @@ CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_NAND=y
 CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
 CONFIG_OF_EMBED=y
+CONFIG_DM=y
 CONFIG_CLK=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_NAND_BRCMNAND_BCMBCA=y

configs/bcm96756_defconfig

@@ -9,7 +9,7 @@ CONFIG_TARGET_BCM96756=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
-CONFIG_DEFAULT_DEVICE_TREE="bcm96756"
+CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcm96756"
 CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_SYS_LOAD_ADDR=0x01000000
 CONFIG_IDENT_STRING=" Broadcom BCM6756"
@@ -17,6 +17,15 @@ CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_NAND=y
 CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
 CONFIG_OF_EMBED=y
+CONFIG_DM=y
 CONFIG_CLK=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_NAND_BRCMNAND_BCMBCA=y

configs/bcm96813_defconfig

@@ -9,13 +9,22 @@ CONFIG_TARGET_BCM96813=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
-CONFIG_DEFAULT_DEVICE_TREE="bcm96813"
+CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcmbca/bcm96813"
 CONFIG_SYS_LOAD_ADDR=0x01000000
 CONFIG_IDENT_STRING=" Broadcom BCM6813"
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_NAND=y
 CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
 CONFIG_OF_EMBED=y
+CONFIG_DM=y
 CONFIG_CLK=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_NAND_BRCMNAND_BCMBCA=y

configs/bcm96855_defconfig

@@ -9,7 +9,7 @@ CONFIG_TARGET_BCM96855=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
-CONFIG_DEFAULT_DEVICE_TREE="bcm96855"
+CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcm96855"
 CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_SYS_LOAD_ADDR=0x01000000
 CONFIG_IDENT_STRING=" Broadcom BCM6855"
@@ -17,6 +17,15 @@ CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_NAND=y
 CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
 CONFIG_OF_EMBED=y
+CONFIG_DM=y
 CONFIG_CLK=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_NAND_BRCMNAND_BCMBCA=y

configs/bcm96856_defconfig

@@ -9,13 +9,22 @@ CONFIG_TARGET_BCM96856=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
-CONFIG_DEFAULT_DEVICE_TREE="bcm96856"
+CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcmbca/bcm96856"
 CONFIG_SYS_LOAD_ADDR=0x01000000
 CONFIG_IDENT_STRING=" Broadcom BCM6856"
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_NAND=y
 CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
 CONFIG_OF_EMBED=y
+CONFIG_DM=y
 CONFIG_CLK=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_NAND_BRCMNAND_BCMBCA=y

configs/bcm96858_defconfig

@@ -9,13 +9,22 @@ CONFIG_TARGET_BCM96858=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
-CONFIG_DEFAULT_DEVICE_TREE="bcm96858"
+CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcmbca/bcm96858"
 CONFIG_SYS_LOAD_ADDR=0x01000000
 CONFIG_IDENT_STRING=" Broadcom BCM6858"
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_NAND=y
 CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
 CONFIG_OF_EMBED=y
+CONFIG_DM=y
 CONFIG_CLK=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_NAND_BRCMNAND_BCMBCA=y

configs/bcm96878_defconfig

@@ -9,7 +9,7 @@ CONFIG_TARGET_BCM96878=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
-CONFIG_DEFAULT_DEVICE_TREE="bcm96878"
+CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcm96878"
 CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_SYS_LOAD_ADDR=0x01000000
 CONFIG_IDENT_STRING=" Broadcom BCM6878"
@@ -17,6 +17,15 @@ CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_NAND=y
 CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
 CONFIG_OF_EMBED=y
+CONFIG_DM=y
 CONFIG_CLK=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_NAND_BRCMNAND_BCMBCA=y

configs/imx8m_data_modul.config

@@ -0,0 +1,221 @@
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_INPUT is not set
+# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
+# CONFIG_SPL_DM_USB is not set
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_ARCH_IMX8M=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_ARM=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOOTCOMMAND="run dmo_update_env ; load ${devtype} ${devnum}:${devpart} ${loadaddr} boot/fitImage && source ${loadaddr}:bootscr-boot.cmd ; reset"
+CONFIG_BOOTCOUNT_BOOTLIMIT=3
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_BKOPS_ENABLE=y
+CONFIG_CMD_BOOTCOUNT=y
+CONFIG_CMD_BTRFS=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_CAT=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_DHCP6=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_FS_UUID=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_KASLRSEED=y
+CONFIG_CMD_LSBLK=y
+CONFIG_CMD_MBR=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_PXE=y
+CONFIG_CMD_READ=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_CMD_SMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_SYSBOOT=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_USB_SDP=y
+CONFIG_CMD_UUID=y
+CONFIG_CMD_WGET=y
+CONFIG_CMD_XXD=y
+CONFIG_CONSOLE_MUX=y
+CONFIG_CRC32_VERIFY=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0x30880000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DFU_MMC=y
+CONFIG_DFU_MTD=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_TIMEOUT=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MTD=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RESET=y
+CONFIG_DM_RNG=y
+CONFIG_DM_RTC=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_THERMAL=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_OFFSET=0xFFFC0000
+CONFIG_ENV_OFFSET_REDUND=0xFFFC0000
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FEC_MXC=y
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_FSL_CAAM=y
+CONFIG_FSL_USDHC=y
+CONFIG_GPIO_HOG=y
+CONFIG_HASH_VERIFY=y
+CONFIG_HUSH_PARSER=y
+CONFIG_I2C_EEPROM=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_IMX_TMU=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_IPV6=y
+CONFIG_IP_DEFRAG=y
+CONFIG_MD5SUM_VERIFY=y
+CONFIG_MII=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_SPEED_MODE_SET=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MTD=y
+CONFIG_MTDIDS_DEFAULT="nor0=flash@0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=flash@0:-(sf)"
+CONFIG_MXC_GPIO=y
+CONFIG_MXC_SPI=y
+CONFIG_MXC_UART=y
+CONFIG_NETCONSOLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_OF_CONTROL=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_PROT_TCP_SACK=y
+CONFIG_REGMAP=y
+CONFIG_RGMII=y
+CONFIG_RTC_M41T62=y
+CONFIG_SF_DEFAULT_SPEED=50000000
+CONFIG_SHA1SUM_VERIFY=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPL=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_MMC_IO_VOLTAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_SYSCON=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090
+CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000
+CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
+CONFIG_SYS_BOOTM_LEN=0x8000000
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20
+CONFIG_SYS_EEPROM_SIZE=16384
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SYS_MMC_ENV_PART=1
+CONFIG_SYS_MONITOR_LEN=1048576
+CONFIG_SYS_PBSIZE=2081
+CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_TEXT_BASE=0x40200000
+CONFIG_TFTP_TSIZE=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_FUNCTION_ACM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Data Modul"
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_HUB_USB251XB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_USE_PREBOOT=y
+CONFIG_VERSION_VARIABLE=y

configs/imx8mm_data_modul_edm_sbc_defconfig

@@ -1,243 +1,39 @@
+#include <configs/imx8m_data_modul.config>
+
 CONFIG_ARM=y
 CONFIG_ARCH_IMX8M=y
-CONFIG_TEXT_BASE=0x40200000
-CONFIG_SYS_MALLOC_LEN=0x1000000
-CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_SF_DEFAULT_SPEED=50000000
-CONFIG_ENV_SIZE=0x40000
-CONFIG_ENV_OFFSET=0xFFFC0000
-CONFIG_IMX_CONFIG="board/data_modul/imx8mm_edm_sbc/imximage.cfg"
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mm-data-modul-edm-sbc"
 CONFIG_TARGET_IMX8MM_DATA_MODUL_EDM_SBC=y
-CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_DM_RESET=y
-CONFIG_SYS_MONITOR_LEN=1048576
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090
-CONFIG_SPL_STACK=0x920000
-CONFIG_SPL_TEXT_BASE=0x7E1000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x910000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
-CONFIG_SYS_BOOTM_LEN=0x8000000
-CONFIG_SYS_LOAD_ADDR=0x60000000
-CONFIG_SPL=y
-CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
-CONFIG_ENV_OFFSET_REDUND=0xFFFC0000
-CONFIG_IMX_BOOTAUX=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_FIT=y
-CONFIG_FIT_EXTERNAL_OFFSET=0x3000
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run dmo_update_env ; load ${devtype} ${devnum}:${devpart} ${loadaddr} boot/fitImage && source ${loadaddr}:bootscr-boot.cmd ; reset"
-CONFIG_USE_PREBOOT=y
-CONFIG_PREBOOT="run dmo_preboot"
-CONFIG_DEFAULT_FDT_FILE="imx8mm-data-modul-edm-sbc.dtb"
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2074
-CONFIG_CONSOLE_MUX=y
-CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_BOARD_LATE_INIT=y
-# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-CONFIG_SPL_LEGACY_IMAGE_FORMAT=y
-CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_HAVE_INIT_STACK=y
-CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
-CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
-CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
-CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
-CONFIG_SPL_I2C=y
-CONFIG_SPL_POWER=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_WATCHDOG=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="u-boot=> "
-# CONFIG_BOOTM_NETBSD is not set
-# CONFIG_BOOTM_PLAN9 is not set
-# CONFIG_BOOTM_RTEMS is not set
-# CONFIG_BOOTM_VXWORKS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_EXPORTENV is not set
-CONFIG_CMD_ERASEENV=y
-CONFIG_CRC32_VERIFY=y
-CONFIG_CMD_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
-CONFIG_SYS_EEPROM_SIZE=16384
-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20
-CONFIG_CMD_MD5SUM=y
-CONFIG_MD5SUM_VERIFY=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_SHA1SUM=y
-CONFIG_SHA1SUM_VERIFY=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_FUSE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_GPT_RENAME=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_LSBLK=y
-CONFIG_CMD_MBR=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_BKOPS_ENABLE=y
-CONFIG_MMC_SPEED_MODE_SET=y
-CONFIG_CMD_MTD=y
-CONFIG_CMD_PART=y
-CONFIG_CMD_READ=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_SDP=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_CAT=y
-CONFIG_CMD_XXD=y
-CONFIG_CMD_DHCP6=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_WGET=y
-CONFIG_CMD_PXE=y
-CONFIG_CMD_BOOTCOUNT=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_GETTIME=y
-CONFIG_CMD_KASLRSEED=y
-CONFIG_CMD_SYSBOOT=y
-CONFIG_CMD_UUID=y
-CONFIG_CMD_PMIC=y
-CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_SMC=y
-CONFIG_HASH_VERIFY=y
-CONFIG_CMD_BTRFS=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_CMD_FS_UUID=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
-CONFIG_MTDIDS_DEFAULT="nor0=flash@0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=flash@0:-(sf)"
-CONFIG_PARTITION_TYPE_GUID=y
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SYS_MMC_ENV_PART=1
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_NETCONSOLE=y
-CONFIG_IP_DEFRAG=y
-CONFIG_TFTP_TSIZE=y
-CONFIG_PROT_TCP_SACK=y
-CONFIG_IPV6=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000
-CONFIG_SPL_CLK_COMPOSITE_CCF=y
-CONFIG_CLK_COMPOSITE_CCF=y
-CONFIG_SPL_CLK_IMX8MM=y
-CONFIG_CLK_IMX8MM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DFU_TFTP=y
-CONFIG_DFU_TIMEOUT=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_MTD=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_BUF_ADDR=0x42800000
-CONFIG_FASTBOOT_BUF_SIZE=0x20000000
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_GPIO_HOG=y
-CONFIG_MXC_GPIO=y
-CONFIG_DM_I2C=y
-# CONFIG_INPUT is not set
-CONFIG_USB_HUB_USB251XB=y
-CONFIG_I2C_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x50
-CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_MMC_IO_VOLTAGE=y
-CONFIG_SPL_MMC_IO_VOLTAGE=y
-CONFIG_MMC_UHS_SUPPORT=y
-CONFIG_MMC_HS400_ES_SUPPORT=y
-CONFIG_MMC_HS400_SUPPORT=y
-CONFIG_FSL_USDHC=y
-CONFIG_MTD=y
-CONFIG_DM_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SFDP_SUPPORT=y
-# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_SPI_FLASH_MTD=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_ANEG_TIMEOUT=20000
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_DM_MDIO=y
-CONFIG_DM_ETH_PHY=y
-CONFIG_FEC_MXC=y
-CONFIG_RGMII=y
-CONFIG_MII=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
-CONFIG_PINCTRL_IMX8M=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_IMX8M_POWER_DOMAIN=y
-CONFIG_DM_PMIC=y
-CONFIG_DM_PMIC_BD71837=y
-CONFIG_SPL_DM_PMIC_BD71837=y
-CONFIG_DM_REGULATOR=y
-CONFIG_SPL_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_BD71837=y
-CONFIG_SPL_DM_REGULATOR_BD71837=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_DM_RNG=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_M41T62=y
-CONFIG_DM_SERIAL=y
-CONFIG_MXC_UART=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_SYSRESET=y
-CONFIG_SPL_SYSRESET=y
-CONFIG_SYSRESET_PSCI=y
-CONFIG_SYSRESET_WATCHDOG=y
-CONFIG_DM_THERMAL=y
-CONFIG_IMX_TMU=y
-CONFIG_USB=y
-# CONFIG_SPL_DM_USB is not set
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Data Modul"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
-CONFIG_USB_FUNCTION_ACM=y
-CONFIG_IMX_WATCHDOG=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_CMD_PCI=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-data-modul-edm-sbc"
+CONFIG_DEFAULT_FDT_FILE="imx8mm-data-modul-edm-sbc.dtb"
+CONFIG_DM_PMIC_BD71837=y
+CONFIG_DM_REGULATOR_BD71837=y
+CONFIG_IMX_CONFIG="board/data_modul/imx8mm_edm_sbc/imximage.cfg"
+CONFIG_NVME_PCI=y
+CONFIG_PCI=y
+CONFIG_PCIE_DW_IMX=y
+CONFIG_PHY=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_IMX8M_PCIE=y
+CONFIG_PREBOOT="run dmo_preboot"
+CONFIG_SDP_LOADADDR=0x60000000
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
+CONFIG_SPL_BSS_START_ADDR=0x910000
+CONFIG_SPL_MAX_SIZE=0x30000
+CONFIG_SPL_CLK_IMX8MM=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_DM_PMIC_BD71837=y
+CONFIG_SPL_DM_REGULATOR_BD71837=y
+CONFIG_SPL_DM_USB=y
+CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y
+CONFIG_SPL_LEGACY_IMAGE_FORMAT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_STACK=0x920000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_HOST=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SYS_LOAD_ADDR=0x60000000

configs/imx8mp_data_modul_edm_sbc_defconfig

@@ -1,272 +1,54 @@
+#include <configs/imx8m_data_modul.config>
+
 CONFIG_ARM=y
 CONFIG_ARCH_IMX8M=y
-CONFIG_TEXT_BASE=0x40200000
-CONFIG_SYS_MALLOC_LEN=0x1000000
-CONFIG_SYS_MALLOC_F_LEN=0x18000
-CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_SF_DEFAULT_SPEED=50000000
-CONFIG_ENV_SIZE=0x40000
-CONFIG_ENV_OFFSET=0xFFFC0000
-CONFIG_DM_GPIO=y
-CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mp-data-modul-edm-sbc"
 CONFIG_TARGET_IMX8MP_DATA_MODUL_EDM_SBC=y
-CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_DM_RESET=y
-CONFIG_SYS_MONITOR_LEN=1048576
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090
-CONFIG_SPL_STACK=0x96fc00
-CONFIG_SPL_TEXT_BASE=0x920000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x96fc00
-CONFIG_SPL_BSS_MAX_SIZE=0x600
-CONFIG_SYS_BOOTM_LEN=0x8000000
-CONFIG_SYS_LOAD_ADDR=0x50000000
-CONFIG_SPL=y
-CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
-CONFIG_DEBUG_UART_BASE=0x30880000
-CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_ENV_OFFSET_REDUND=0xFFFC0000
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI=y
-CONFIG_IMX_BOOTAUX=y
-CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
-CONFIG_DEBUG_UART=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_FIT=y
-CONFIG_FIT_EXTERNAL_OFFSET=0x3000
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run dmo_update_env ; load ${devtype} ${devnum}:${devpart} ${loadaddr} boot/fitImage && source ${loadaddr}:bootscr-boot.cmd ; reset"
-CONFIG_USE_PREBOOT=y
-CONFIG_DEFAULT_FDT_FILE="imx8mp-data-modul-edm-sbc.dtb"
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2081
-CONFIG_CONSOLE_MUX=y
-CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_BOARD_LATE_INIT=y
-CONFIG_SPL_MAX_SIZE=0x25000
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_BOOTROM_SUPPORT=y
-# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_HAVE_INIT_STACK=y
-CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
-CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x4c000000
-CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
-CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
-CONFIG_SPL_I2C=y
-CONFIG_SPL_DM_SPI_FLASH=y
-CONFIG_SPL_POWER=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x58000
-CONFIG_SPL_WATCHDOG=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="u-boot=> "
-# CONFIG_BOOTM_NETBSD is not set
-# CONFIG_BOOTM_PLAN9 is not set
-# CONFIG_BOOTM_RTEMS is not set
-# CONFIG_BOOTM_VXWORKS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_EXPORTENV is not set
-CONFIG_CMD_ERASEENV=y
-CONFIG_CRC32_VERIFY=y
-CONFIG_CMD_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
-CONFIG_SYS_EEPROM_SIZE=16384
-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20
-CONFIG_CMD_MD5SUM=y
-CONFIG_MD5SUM_VERIFY=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_SHA1SUM=y
-CONFIG_SHA1SUM_VERIFY=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_FUSE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_GPT_RENAME=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_LSBLK=y
-CONFIG_CMD_MBR=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_BKOPS_ENABLE=y
-CONFIG_MMC_SPEED_MODE_SET=y
-CONFIG_CMD_MTD=y
-CONFIG_CMD_PART=y
-CONFIG_CMD_READ=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_SDP=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_CAT=y
-CONFIG_CMD_XXD=y
-CONFIG_CMD_DHCP6=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_WGET=y
-CONFIG_CMD_PXE=y
-CONFIG_CMD_BOOTCOUNT=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_GETTIME=y
-CONFIG_CMD_KASLRSEED=y
-CONFIG_CMD_SYSBOOT=y
-CONFIG_CMD_UUID=y
-CONFIG_CMD_PMIC=y
-CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_SMC=y
-CONFIG_HASH_VERIFY=y
-CONFIG_CMD_BTRFS=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_CMD_FS_UUID=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
-CONFIG_MTDIDS_DEFAULT="nor0=flash@0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=flash@0:-(sf)"
-CONFIG_PARTITION_TYPE_GUID=y
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_NOWHERE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SYS_MMC_ENV_PART=1
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_NETCONSOLE=y
-CONFIG_IP_DEFRAG=y
-CONFIG_TFTP_TSIZE=y
-CONFIG_PROT_TCP_SACK=y
-CONFIG_IPV6=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000
-CONFIG_SPL_CLK_COMPOSITE_CCF=y
-CONFIG_CLK_COMPOSITE_CCF=y
-CONFIG_SPL_CLK_IMX8MP=y
 CONFIG_CLK_IMX8MP=y
-CONFIG_FSL_CAAM=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mp-data-modul-edm-sbc"
+CONFIG_DEFAULT_FDT_FILE="imx8mp-data-modul-edm-sbc.dtb"
+CONFIG_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR_PCA9450=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y
 CONFIG_IMX8M_DRAM_INLINE_ECC=y
-CONFIG_DFU_TFTP=y
-CONFIG_DFU_TIMEOUT=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_MTD=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_BUF_ADDR=0x42800000
-CONFIG_FASTBOOT_BUF_SIZE=0x20000000
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_GPIO_HOG=y
-CONFIG_SPL_GPIO_HOG=y
-CONFIG_MXC_GPIO=y
-CONFIG_DM_I2C=y
-# CONFIG_INPUT is not set
 CONFIG_LED=y
 CONFIG_LED_BLINK=y
 CONFIG_LED_GPIO=y
-CONFIG_USB_HUB_USB251XB=y
-CONFIG_I2C_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x50
-CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_MMC_IO_VOLTAGE=y
-CONFIG_SPL_MMC_IO_VOLTAGE=y
-CONFIG_MMC_UHS_SUPPORT=y
-CONFIG_SPL_MMC_UHS_SUPPORT=y
-CONFIG_MMC_HS400_ES_SUPPORT=y
-CONFIG_MMC_HS400_SUPPORT=y
-CONFIG_FSL_USDHC=y
-CONFIG_MTD=y
-CONFIG_DM_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SFDP_SUPPORT=y
-# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_SPI_FLASH_MTD=y
-CONFIG_PHY_ANEG_TIMEOUT=20000
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_IMX8MQ_USB=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_DM_MDIO=y
-CONFIG_DM_ETH_PHY=y
-CONFIG_DWC_ETH_QOS=y
-CONFIG_DWC_ETH_QOS_IMX=y
-CONFIG_FEC_MXC=y
-CONFIG_RGMII=y
-CONFIG_MII=y
-CONFIG_PHY_IMX8MQ_USB=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
-CONFIG_PINCTRL_IMX8M=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_IMX8M_POWER_DOMAIN=y
-CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y
-CONFIG_DM_PMIC=y
-CONFIG_DM_PMIC_PCA9450=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_BSS_MAX_SIZE=0x400
+CONFIG_SPL_BSS_START_ADDR=0x96fc00
+CONFIG_SPL_CLK_IMX8MP=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x4c000000
 CONFIG_SPL_DM_PMIC_PCA9450=y
-CONFIG_DM_REGULATOR=y
-CONFIG_SPL_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_PCA9450=y
 CONFIG_SPL_DM_REGULATOR_PCA9450=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_DM_RNG=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_M41T62=y
-CONFIG_DM_SERIAL=y
-CONFIG_MXC_UART=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_SYSRESET=y
-CONFIG_SPL_SYSRESET=y
-CONFIG_SYSRESET_PSCI=y
-CONFIG_SYSRESET_WATCHDOG=y
-CONFIG_DM_THERMAL=y
-CONFIG_IMX_TMU=y
-CONFIG_USB=y
-# CONFIG_SPL_DM_USB is not set
-CONFIG_DM_USB_GADGET=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
-CONFIG_USB_EHCI_HCD=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_GPIO_HOG=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_SPL_MAX_SIZE=0x25000
+CONFIG_SPL_MMC_UHS_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_STACK=0x96fc00
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_TEXT_BASE=0x920000
+CONFIG_SYS_LOAD_ADDR=0x50000000
+CONFIG_SYS_MALLOC_F_LEN=0x18000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x58000
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GENERIC=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_ASIX=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Data Modul"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_USB_FUNCTION_ACM=y
 CONFIG_USB_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETH_CDC=y
-CONFIG_IMX_WATCHDOG=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
+CONFIG_USB_XHCI_HCD=y

configs/sifive_unmatched_defconfig

@@ -36,6 +36,7 @@ CONFIG_DISPLAY_BOARDINFO=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_ID_EEPROM=y
 CONFIG_PCI_INIT_R=y
+CONFIG_PCI_REGION_MULTI_ENTRY=y
 CONFIG_SPL_MAX_SIZE=0x100000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_HAVE_INIT_STACK=y
@@ -43,6 +44,7 @@ CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_SPI_LOAD=y
+CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_EEPROM=y
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_PWM=y

drivers/mtd/nand/raw/Kconfig

@@ -133,36 +133,12 @@ config NAND_BRCMNAND_6368
 	help
 	  Enable support for broadcom nand driver on bcm6368.
 
-config NAND_BRCMNAND_6753
-	bool "Support Broadcom NAND controller on bcm6753"
-	depends on NAND_BRCMNAND && BCM6855
-	help
-	  Enable support for broadcom nand driver on bcm6753.
-
-config NAND_BRCMNAND_68360
-	bool "Support Broadcom NAND controller on bcm68360"
-	depends on NAND_BRCMNAND && BCM6856
-	help
-	  Enable support for broadcom nand driver on bcm68360.
-
 config NAND_BRCMNAND_6838
 	bool "Support Broadcom NAND controller on bcm6838"
 	depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838
 	help
 	  Enable support for broadcom nand driver on bcm6838.
 
-config NAND_BRCMNAND_6858
-	bool "Support Broadcom NAND controller on bcm6858"
-	depends on NAND_BRCMNAND && BCM6858
-	help
-	  Enable support for broadcom nand driver on bcm6858.
-
-config NAND_BRCMNAND_63158
-	bool "Support Broadcom NAND controller on bcm63158"
-	depends on NAND_BRCMNAND && BCM63158
-	help
-	  Enable support for broadcom nand driver on bcm63158.
-
 config NAND_BRCMNAND_IPROC
 	bool "Support Broadcom NAND controller on the iproc family"
 	depends on NAND_BRCMNAND

drivers/mtd/nand/raw/brcmnand/Makefile

@@ -1,11 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 
 obj-$(CONFIG_NAND_BRCMNAND_6368) += bcm6368_nand.o
-obj-$(CONFIG_NAND_BRCMNAND_63158) += bcm63158_nand.o
-obj-$(CONFIG_NAND_BRCMNAND_6753) += bcm6753_nand.o
-obj-$(CONFIG_NAND_BRCMNAND_68360) += bcm68360_nand.o
 obj-$(CONFIG_NAND_BRCMNAND_6838) += bcm6838_nand.o
-obj-$(CONFIG_NAND_BRCMNAND_6858) += bcm6858_nand.o
 obj-$(CONFIG_NAND_BRCMNAND_BCMBCA) += bcmbca_nand.o
 obj-$(CONFIG_NAND_BRCMNAND_IPROC) += iproc_nand.o
 obj-$(CONFIG_NAND_BRCMNAND) += brcmnand.o

drivers/mtd/nand/raw/brcmnand/bcm63158_nand.c

@@ -1,125 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-
-#include <asm/io.h>
-#include <memalign.h>
-#include <nand.h>
-#include <linux/bitops.h>
-#include <linux/err.h>
-#include <linux/errno.h>
-#include <linux/io.h>
-#include <linux/ioport.h>
-#include <dm.h>
-#include <linux/printk.h>
-
-#include "brcmnand.h"
-
-struct bcm63158_nand_soc {
-	struct brcmnand_soc soc;
-	void __iomem *base;
-};
-
-#define BCM63158_NAND_INT		0x00
-#define BCM63158_NAND_STATUS_SHIFT	0
-#define BCM63158_NAND_STATUS_MASK	(0xfff << BCM63158_NAND_STATUS_SHIFT)
-
-#define BCM63158_NAND_INT_EN		0x04
-#define BCM63158_NAND_ENABLE_SHIFT	0
-#define BCM63158_NAND_ENABLE_MASK	(0xffff << BCM63158_NAND_ENABLE_SHIFT)
-
-enum {
-	BCM63158_NP_READ		= BIT(0),
-	BCM63158_BLOCK_ERASE	= BIT(1),
-	BCM63158_COPY_BACK	= BIT(2),
-	BCM63158_PAGE_PGM	= BIT(3),
-	BCM63158_CTRL_READY	= BIT(4),
-	BCM63158_DEV_RBPIN	= BIT(5),
-	BCM63158_ECC_ERR_UNC	= BIT(6),
-	BCM63158_ECC_ERR_CORR	= BIT(7),
-};
-
-static bool bcm63158_nand_intc_ack(struct brcmnand_soc *soc)
-{
-	struct bcm63158_nand_soc *priv =
-			container_of(soc, struct bcm63158_nand_soc, soc);
-	void __iomem *mmio = priv->base + BCM63158_NAND_INT;
-	u32 val = brcmnand_readl(mmio);
-
-	if (val & (BCM63158_CTRL_READY << BCM63158_NAND_STATUS_SHIFT)) {
-		/* Ack interrupt */
-		val &= ~BCM63158_NAND_STATUS_MASK;
-		val |= BCM63158_CTRL_READY << BCM63158_NAND_STATUS_SHIFT;
-		brcmnand_writel(val, mmio);
-		return true;
-	}
-
-	return false;
-}
-
-static void bcm63158_nand_intc_set(struct brcmnand_soc *soc, bool en)
-{
-	struct bcm63158_nand_soc *priv =
-			container_of(soc, struct bcm63158_nand_soc, soc);
-	void __iomem *mmio = priv->base + BCM63158_NAND_INT_EN;
-	u32 val = brcmnand_readl(mmio);
-
-	/* Don't ack any interrupts */
-	val &= ~BCM63158_NAND_STATUS_MASK;
-
-	if (en)
-		val |= BCM63158_CTRL_READY << BCM63158_NAND_ENABLE_SHIFT;
-	else
-		val &= ~(BCM63158_CTRL_READY << BCM63158_NAND_ENABLE_SHIFT);
-
-	brcmnand_writel(val, mmio);
-}
-
-static int bcm63158_nand_probe(struct udevice *dev)
-{
-	struct udevice *pdev = dev;
-	struct bcm63158_nand_soc *priv = dev_get_priv(dev);
-	struct brcmnand_soc *soc;
-	struct resource res;
-
-	soc = &priv->soc;
-
-	dev_read_resource_byname(pdev, "nand-int-base", &res);
-	priv->base = devm_ioremap(dev, res.start, resource_size(&res));
-	if (IS_ERR(priv->base))
-		return PTR_ERR(priv->base);
-
-	soc->ctlrdy_ack = bcm63158_nand_intc_ack;
-	soc->ctlrdy_set_enabled = bcm63158_nand_intc_set;
-
-	/* Disable and ack all interrupts  */
-	brcmnand_writel(0, priv->base + BCM63158_NAND_INT_EN);
-	brcmnand_writel(0, priv->base + BCM63158_NAND_INT);
-
-	return brcmnand_probe(pdev, soc);
-}
-
-static const struct udevice_id bcm63158_nand_dt_ids[] = {
-	{
-		.compatible = "brcm,nand-bcm63158",
-	},
-	{ /* sentinel */ }
-};
-
-U_BOOT_DRIVER(bcm63158_nand) = {
-	.name = "bcm63158-nand",
-	.id = UCLASS_MTD,
-	.of_match = bcm63158_nand_dt_ids,
-	.probe = bcm63158_nand_probe,
-	.priv_auto	= sizeof(struct bcm63158_nand_soc),
-};
-
-void board_nand_init(void)
-{
-	struct udevice *dev;
-	int ret;
-
-	ret = uclass_get_device_by_driver(UCLASS_MTD,
-					  DM_DRIVER_GET(bcm63158_nand), &dev);
-	if (ret && ret != -ENODEV)
-		pr_err("Failed to initialize %s. (error %d)\n", dev->name,
-		       ret);
-}

drivers/mtd/nand/raw/brcmnand/bcm6753_nand.c

@@ -1,123 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-
-#include <asm/io.h>
-#include <memalign.h>
-#include <nand.h>
-#include <linux/bitops.h>
-#include <linux/errno.h>
-#include <linux/io.h>
-#include <linux/ioport.h>
-#include <dm.h>
-
-#include "brcmnand.h"
-
-struct bcm6753_nand_soc {
-	struct brcmnand_soc soc;
-	void __iomem *base;
-};
-
-#define BCM6753_NAND_INT		0x00
-#define BCM6753_NAND_STATUS_SHIFT	0
-#define BCM6753_NAND_STATUS_MASK	(0xfff << BCM6753_NAND_STATUS_SHIFT)
-
-#define BCM6753_NAND_INT_EN		0x04
-#define BCM6753_NAND_ENABLE_SHIFT	0
-#define BCM6753_NAND_ENABLE_MASK	(0xffff << BCM6753_NAND_ENABLE_SHIFT)
-
-enum {
-	BCM6753_NP_READ		= BIT(0),
-	BCM6753_BLOCK_ERASE	= BIT(1),
-	BCM6753_COPY_BACK	= BIT(2),
-	BCM6753_PAGE_PGM	= BIT(3),
-	BCM6753_CTRL_READY	= BIT(4),
-	BCM6753_DEV_RBPIN	= BIT(5),
-	BCM6753_ECC_ERR_UNC	= BIT(6),
-	BCM6753_ECC_ERR_CORR	= BIT(7),
-};
-
-static bool bcm6753_nand_intc_ack(struct brcmnand_soc *soc)
-{
-	struct bcm6753_nand_soc *priv =
-			container_of(soc, struct bcm6753_nand_soc, soc);
-	void __iomem *mmio = priv->base + BCM6753_NAND_INT;
-	u32 val = brcmnand_readl(mmio);
-
-	if (val & (BCM6753_CTRL_READY << BCM6753_NAND_STATUS_SHIFT)) {
-		/* Ack interrupt */
-		val &= ~BCM6753_NAND_STATUS_MASK;
-		val |= BCM6753_CTRL_READY << BCM6753_NAND_STATUS_SHIFT;
-		brcmnand_writel(val, mmio);
-		return true;
-	}
-
-	return false;
-}
-
-static void bcm6753_nand_intc_set(struct brcmnand_soc *soc, bool en)
-{
-	struct bcm6753_nand_soc *priv =
-			container_of(soc, struct bcm6753_nand_soc, soc);
-	void __iomem *mmio = priv->base + BCM6753_NAND_INT_EN;
-	u32 val = brcmnand_readl(mmio);
-
-	/* Don't ack any interrupts */
-	val &= ~BCM6753_NAND_STATUS_MASK;
-
-	if (en)
-		val |= BCM6753_CTRL_READY << BCM6753_NAND_ENABLE_SHIFT;
-	else
-		val &= ~(BCM6753_CTRL_READY << BCM6753_NAND_ENABLE_SHIFT);
-
-	brcmnand_writel(val, mmio);
-}
-
-static int bcm6753_nand_probe(struct udevice *dev)
-{
-	struct udevice *pdev = dev;
-	struct bcm6753_nand_soc *priv = dev_get_priv(dev);
-	struct brcmnand_soc *soc;
-	struct resource res;
-
-	soc = &priv->soc;
-
-	dev_read_resource_byname(pdev, "nand-int-base", &res);
-	priv->base = devm_ioremap(dev, res.start, resource_size(&res));
-	if (IS_ERR(priv->base))
-		return PTR_ERR(priv->base);
-
-	soc->ctlrdy_ack = bcm6753_nand_intc_ack;
-	soc->ctlrdy_set_enabled = bcm6753_nand_intc_set;
-
-	/* Disable and ack all interrupts  */
-	brcmnand_writel(0, priv->base + BCM6753_NAND_INT_EN);
-	brcmnand_writel(0, priv->base + BCM6753_NAND_INT);
-
-	return brcmnand_probe(pdev, soc);
-}
-
-static const struct udevice_id bcm6753_nand_dt_ids[] = {
-	{
-		.compatible = "brcm,nand-bcm6753",
-	},
-	{ /* sentinel */ }
-};
-
-U_BOOT_DRIVER(bcm6753_nand) = {
-	.name = "bcm6753-nand",
-	.id = UCLASS_MTD,
-	.of_match = bcm6753_nand_dt_ids,
-	.probe = bcm6753_nand_probe,
-	.priv_auto = sizeof(struct bcm6753_nand_soc),
-};
-
-void board_nand_init(void)
-{
-	struct udevice *dev;
-	int ret;
-
-	ret = uclass_get_device_by_driver(UCLASS_MTD,
-					  DM_DRIVER_GET(bcm6753_nand), &dev);
-	if (ret && ret != -ENODEV)
-		pr_err("Failed to initialize %s. (error %d)\n", dev->name,
-		       ret);
-}

drivers/mtd/nand/raw/brcmnand/bcm68360_nand.c

@@ -1,124 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-
-#include <asm/io.h>
-#include <memalign.h>
-#include <nand.h>
-#include <linux/bitops.h>
-#include <linux/errno.h>
-#include <linux/io.h>
-#include <linux/ioport.h>
-#include <dm.h>
-#include <linux/printk.h>
-
-#include "brcmnand.h"
-
-struct bcm68360_nand_soc {
-	struct brcmnand_soc soc;
-	void __iomem *base;
-};
-
-#define BCM68360_NAND_INT		0x00
-#define BCM68360_NAND_STATUS_SHIFT	0
-#define BCM68360_NAND_STATUS_MASK	(0xfff << BCM68360_NAND_STATUS_SHIFT)
-
-#define BCM68360_NAND_INT_EN		0x04
-#define BCM68360_NAND_ENABLE_SHIFT	0
-#define BCM68360_NAND_ENABLE_MASK	(0xffff << BCM68360_NAND_ENABLE_SHIFT)
-
-enum {
-	BCM68360_NP_READ		= BIT(0),
-	BCM68360_BLOCK_ERASE	= BIT(1),
-	BCM68360_COPY_BACK	= BIT(2),
-	BCM68360_PAGE_PGM	= BIT(3),
-	BCM68360_CTRL_READY	= BIT(4),
-	BCM68360_DEV_RBPIN	= BIT(5),
-	BCM68360_ECC_ERR_UNC	= BIT(6),
-	BCM68360_ECC_ERR_CORR	= BIT(7),
-};
-
-static bool bcm68360_nand_intc_ack(struct brcmnand_soc *soc)
-{
-	struct bcm68360_nand_soc *priv =
-			container_of(soc, struct bcm68360_nand_soc, soc);
-	void __iomem *mmio = priv->base + BCM68360_NAND_INT;
-	u32 val = brcmnand_readl(mmio);
-
-	if (val & (BCM68360_CTRL_READY << BCM68360_NAND_STATUS_SHIFT)) {
-		/* Ack interrupt */
-		val &= ~BCM68360_NAND_STATUS_MASK;
-		val |= BCM68360_CTRL_READY << BCM68360_NAND_STATUS_SHIFT;
-		brcmnand_writel(val, mmio);
-		return true;
-	}
-
-	return false;
-}
-
-static void bcm68360_nand_intc_set(struct brcmnand_soc *soc, bool en)
-{
-	struct bcm68360_nand_soc *priv =
-			container_of(soc, struct bcm68360_nand_soc, soc);
-	void __iomem *mmio = priv->base + BCM68360_NAND_INT_EN;
-	u32 val = brcmnand_readl(mmio);
-
-	/* Don't ack any interrupts */
-	val &= ~BCM68360_NAND_STATUS_MASK;
-
-	if (en)
-		val |= BCM68360_CTRL_READY << BCM68360_NAND_ENABLE_SHIFT;
-	else
-		val &= ~(BCM68360_CTRL_READY << BCM68360_NAND_ENABLE_SHIFT);
-
-	brcmnand_writel(val, mmio);
-}
-
-static int bcm68360_nand_probe(struct udevice *dev)
-{
-	struct udevice *pdev = dev;
-	struct bcm68360_nand_soc *priv = dev_get_priv(dev);
-	struct brcmnand_soc *soc;
-	struct resource res;
-
-	soc = &priv->soc;
-
-	dev_read_resource_byname(pdev, "nand-int-base", &res);
-	priv->base = devm_ioremap(dev, res.start, resource_size(&res));
-	if (IS_ERR(priv->base))
-		return PTR_ERR(priv->base);
-
-	soc->ctlrdy_ack = bcm68360_nand_intc_ack;
-	soc->ctlrdy_set_enabled = bcm68360_nand_intc_set;
-
-	/* Disable and ack all interrupts  */
-	brcmnand_writel(0, priv->base + BCM68360_NAND_INT_EN);
-	brcmnand_writel(0, priv->base + BCM68360_NAND_INT);
-
-	return brcmnand_probe(pdev, soc);
-}
-
-static const struct udevice_id bcm68360_nand_dt_ids[] = {
-	{
-		.compatible = "brcm,nand-bcm68360",
-	},
-	{ /* sentinel */ }
-};
-
-U_BOOT_DRIVER(bcm68360_nand) = {
-	.name = "bcm68360-nand",
-	.id = UCLASS_MTD,
-	.of_match = bcm68360_nand_dt_ids,
-	.probe = bcm68360_nand_probe,
-	.priv_auto	= sizeof(struct bcm68360_nand_soc),
-};
-
-void board_nand_init(void)
-{
-	struct udevice *dev;
-	int ret;
-
-	ret = uclass_get_device_by_driver(UCLASS_MTD,
-					  DM_DRIVER_GET(bcm68360_nand), &dev);
-	if (ret && ret != -ENODEV)
-		pr_err("Failed to initialize %s. (error %d)\n", dev->name,
-		       ret);
-}

drivers/mtd/nand/raw/brcmnand/bcm6858_nand.c

@@ -1,125 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-
-#include <asm/io.h>
-#include <memalign.h>
-#include <nand.h>
-#include <linux/bitops.h>
-#include <linux/err.h>
-#include <linux/errno.h>
-#include <linux/io.h>
-#include <linux/ioport.h>
-#include <dm.h>
-#include <linux/printk.h>
-
-#include "brcmnand.h"
-
-struct bcm6858_nand_soc {
-	struct brcmnand_soc soc;
-	void __iomem *base;
-};
-
-#define BCM6858_NAND_INT		0x00
-#define BCM6858_NAND_STATUS_SHIFT	0
-#define BCM6858_NAND_STATUS_MASK	(0xfff << BCM6858_NAND_STATUS_SHIFT)
-
-#define BCM6858_NAND_INT_EN		0x04
-#define BCM6858_NAND_ENABLE_SHIFT	0
-#define BCM6858_NAND_ENABLE_MASK	(0xffff << BCM6858_NAND_ENABLE_SHIFT)
-
-enum {
-	BCM6858_NP_READ		= BIT(0),
-	BCM6858_BLOCK_ERASE	= BIT(1),
-	BCM6858_COPY_BACK	= BIT(2),
-	BCM6858_PAGE_PGM	= BIT(3),
-	BCM6858_CTRL_READY	= BIT(4),
-	BCM6858_DEV_RBPIN	= BIT(5),
-	BCM6858_ECC_ERR_UNC	= BIT(6),
-	BCM6858_ECC_ERR_CORR	= BIT(7),
-};
-
-static bool bcm6858_nand_intc_ack(struct brcmnand_soc *soc)
-{
-	struct bcm6858_nand_soc *priv =
-			container_of(soc, struct bcm6858_nand_soc, soc);
-	void __iomem *mmio = priv->base + BCM6858_NAND_INT;
-	u32 val = brcmnand_readl(mmio);
-
-	if (val & (BCM6858_CTRL_READY << BCM6858_NAND_STATUS_SHIFT)) {
-		/* Ack interrupt */
-		val &= ~BCM6858_NAND_STATUS_MASK;
-		val |= BCM6858_CTRL_READY << BCM6858_NAND_STATUS_SHIFT;
-		brcmnand_writel(val, mmio);
-		return true;
-	}
-
-	return false;
-}
-
-static void bcm6858_nand_intc_set(struct brcmnand_soc *soc, bool en)
-{
-	struct bcm6858_nand_soc *priv =
-			container_of(soc, struct bcm6858_nand_soc, soc);
-	void __iomem *mmio = priv->base + BCM6858_NAND_INT_EN;
-	u32 val = brcmnand_readl(mmio);
-
-	/* Don't ack any interrupts */
-	val &= ~BCM6858_NAND_STATUS_MASK;
-
-	if (en)
-		val |= BCM6858_CTRL_READY << BCM6858_NAND_ENABLE_SHIFT;
-	else
-		val &= ~(BCM6858_CTRL_READY << BCM6858_NAND_ENABLE_SHIFT);
-
-	brcmnand_writel(val, mmio);
-}
-
-static int bcm6858_nand_probe(struct udevice *dev)
-{
-	struct udevice *pdev = dev;
-	struct bcm6858_nand_soc *priv = dev_get_priv(dev);
-	struct brcmnand_soc *soc;
-	struct resource res;
-
-	soc = &priv->soc;
-
-	dev_read_resource_byname(pdev, "nand-int-base", &res);
-	priv->base = devm_ioremap(dev, res.start, resource_size(&res));
-	if (IS_ERR(priv->base))
-		return PTR_ERR(priv->base);
-
-	soc->ctlrdy_ack = bcm6858_nand_intc_ack;
-	soc->ctlrdy_set_enabled = bcm6858_nand_intc_set;
-
-	/* Disable and ack all interrupts  */
-	brcmnand_writel(0, priv->base + BCM6858_NAND_INT_EN);
-	brcmnand_writel(0, priv->base + BCM6858_NAND_INT);
-
-	return brcmnand_probe(pdev, soc);
-}
-
-static const struct udevice_id bcm6858_nand_dt_ids[] = {
-	{
-		.compatible = "brcm,nand-bcm6858",
-	},
-	{ /* sentinel */ }
-};
-
-U_BOOT_DRIVER(bcm6858_nand) = {
-	.name = "bcm6858-nand",
-	.id = UCLASS_MTD,
-	.of_match = bcm6858_nand_dt_ids,
-	.probe = bcm6858_nand_probe,
-	.priv_auto	= sizeof(struct bcm6858_nand_soc),
-};
-
-void board_nand_init(void)
-{
-	struct udevice *dev;
-	int ret;
-
-	ret = uclass_get_device_by_driver(UCLASS_MTD,
-					  DM_DRIVER_GET(bcm6858_nand), &dev);
-	if (ret && ret != -ENODEV)
-		pr_err("Failed to initialize %s. (error %d)\n", dev->name,
-		       ret);
-}

drivers/mtd/nand/raw/brcmnand/brcmnand.c

@@ -1071,8 +1071,8 @@ static int bcmnand_ctrl_poll_status(struct brcmnand_controller *ctrl,
 	if ((val & mask) == expected_val)
 		return 0;
 
-	dev_warn(ctrl->dev, "timeout on status poll (expected %x got %x)\n",
-		 expected_val, val & mask);
+	dev_err(ctrl->dev, "timeout on status poll (expected %x got %x)\n",
+		expected_val, val & mask);
 
 	return -ETIMEDOUT;
 }
@@ -2032,7 +2032,7 @@ try_dmaread:
 				return err;
 		}
 
-		dev_dbg(ctrl->dev, "uncorrectable error at 0x%llx\n",
+		dev_err(ctrl->dev, "uncorrectable error at 0x%llx\n",
 			(unsigned long long)err_addr);
 		mtd->ecc_stats.failed++;
 		/* NAND layer expects zero on ECC errors */
@@ -2793,9 +2793,17 @@ int brcmnand_probe(struct udevice *dev, struct brcmnand_soc *soc)
 	nand_hw_control_init(&ctrl->controller);
 	INIT_LIST_HEAD(&ctrl->host_list);
 
+#ifdef CONFIG_NAND_BRCMNAND_BCMBCA
+	/*
+	 * BCMBCA platform does not use non-linux parameter-page-big-endian dts property,
+	 * param page data is little endian
+	 */
+	ctrl->parameter_page_big_endian = 0;
+#else
 	/* Is parameter page in big endian ? */
 	ctrl->parameter_page_big_endian =
 	    dev_read_u32_default(dev, "parameter-page-big-endian", 1);
+#endif
 
 	/* NAND register range */
 #ifndef __UBOOT__

dts/upstream/src/arm64/ti/k3-j7200-som-p0.dtsi

@@ -124,7 +124,6 @@
 	};
 
 	mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
-		bootph-all;
 		pinctrl-single,pins = <
 			J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
 			J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */

include/configs/imx8mm_data_modul_edm_sbc.h

@@ -34,7 +34,7 @@
 #define CFG_SYS_FSL_ESDHC_ADDR	0
 
 #define CFG_EXTRA_ENV_SETTINGS						\
-	"altbootcmd=setenv devpart 2 && run bootcmd ; reset\0"		\
+	"altbootcmd=run bootcmd\0"					\
 	"bootlimit=3\0"							\
 	"devtype=mmc\0"							\
 	"devpart=1\0"							\

include/configs/imx8mp_data_modul_edm_sbc.h

@@ -24,7 +24,7 @@
 #define FEC_QUIRK_ENET_MAC
 
 #define CFG_EXTRA_ENV_SETTINGS						\
-	"altbootcmd=setenv devpart 2 && run bootcmd ; reset\0"		\
+	"altbootcmd=run bootcmd\0"					\
 	"bootlimit=3\0"							\
 	"devtype=mmc\0"							\
 	"devpart=1\0"							\

test/cmd/wget.c

@@ -19,7 +19,7 @@
 #include <dm/test.h>
 #include <dm/device-internal.h>
 #include <dm/uclass-internal.h>
-#include <test/lib.h>
+#include <test/cmd.h>
 #include <test/test.h>
 #include <test/ut.h>
 
@@ -215,6 +215,10 @@ static int sb_http_handler(struct udevice *dev, void *packet,
 
 static int net_test_wget(struct unit_test_state *uts)
 {
+	char *prev_ethact = env_get("ethact");
+	char *prev_ethrotate = env_get("ethrotate");
+	char *prev_loadaddr = env_get("loadaddr");
+
 	sandbox_eth_set_tx_handler(0, sb_http_handler);
 	sandbox_eth_set_priv(0, uts);
 
@@ -232,6 +236,10 @@ static int net_test_wget(struct unit_test_state *uts)
 	ut_assert_nextline("md5 for 00020000 ... 0002001c ==> 847d5e7320a27462e90bc1ed75eb8cd8");
 	ut_assert_console_end();
 
+	env_set("ethact", prev_ethact);
+	env_set("ethrotate", prev_ethrotate);
+	env_set("loadaddr", prev_loadaddr);
+
 	return 0;
 }
-LIB_TEST(net_test_wget, UTF_CONSOLE);
+CMD_TEST(net_test_wget, UTF_CONSOLE);