pickman: Record cherry-pick of 5 commits from us/next

- 91bc909d31 spl: increase SPL_SYS_MALLOC_SIZE when using BIOSEMU on RISC-V
- afc52da894 configs: SiFive Unmatched: enable 'env erase' sub-command
- 185986caeb configs: visionfive2: re-enable SPL_SYS_MMCSD_RAW_MODE
- bdca70632d configs: enable CONFIG_PCI_REGION_MULTI_ENTRY=y in sifive_unmatched_defconfig
- b51b97e9be Merge https://source.denx.de/u-boot/custodians/u-boot-riscv

.pickman-history

@@ -232,3 +232,74 @@ The branch `cherry-06b8aafd681` was created based on `ci/master` but is identica
 
 ---
 
+## 2025-12-16: us/next
+
+Branch: cherry-91bc909d317
+
+Commits:
+- 91bc909d317 spl: increase SPL_SYS_MALLOC_SIZE when using BIOSEMU on RISC-V
+- afc52da8946 configs: SiFive Unmatched: enable 'env erase' sub-command
+- 185986caebf configs: visionfive2: re-enable SPL_SYS_MMCSD_RAW_MODE
+- bdca70632da configs: enable CONFIG_PCI_REGION_MULTI_ENTRY=y in sifive_unmatched_defconfig
+- b51b97e9be1 Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
+
+### Conversation log
+The repository state is clean. Now let me create and checkout a new branch based on ci/master:
+
+Now let me cherry-pick each commit in order. Let me start with the first commit:
+
+There's a conflict. Let me examine it:
+
+I can see the conflict. The HEAD has a more general `RISCV` condition with a larger size (0x800000), while the commit being cherry-picked adds a more specific `BIOSEMU && RISCV` condition with 0x180000. Since HEAD already has a larger allocation for RISCV, the incoming change is redundant. Let me resolve this by keeping the HEAD version since it already provides sufficient malloc size for RISCV:
+
+The commit became empty because the HEAD already has a better solution. Let me skip this commit and move to the next one:
+
+Now let me cherry-pick the second commit:
+
+Second commit applied successfully. Now the third commit:
+
+This commit is also already applied. Let me skip it:
+
+Now the fourth commit:
+
+Fourth commit applied. Now the fifth commit which is a merge commit:
+
+There's a conflict. Let me examine it:
+
+Same conflict as before - HEAD already has the larger allocation for RISCV. Let me resolve by keeping the HEAD version:
+
+This merge commit also became empty. Let me skip it:
+
+Now let me verify the results with git log:
+
+I see that only 2 commits were applied (the other 3 were already present in ci/master or resolved to empty). Now let me run the build verification:
+
+The build succeeded. Let me provide a summary:
+
+## Final Status
+
+### Cherry-Pick Results
+
+| Commit | Description | Result |
+|--------|-------------|--------|
+| 91bc909d317 | spl: increase SPL_SYS_MALLOC_SIZE when using BIOSEMU on RISC-V | **Skipped** - Already applied (ci/master has `0x800000 if RISCV` which supersedes this) |
+| afc52da8946 | configs: SiFive Unmatched: enable 'env erase' sub-command | **Applied** ✓ |
+| 185986caebf | configs: visionfive2: re-enable SPL_SYS_MMCSD_RAW_MODE | **Skipped** - Already applied |
+| bdca70632da | configs: enable CONFIG_PCI_REGION_MULTI_ENTRY=y in sifive_unmatched_defconfig | **Applied** ✓ |
+| b51b97e9be1 | Merge https://source.denx.de/u-boot/custodians/u-boot-riscv | **Skipped** - Already applied (merge commit content already in ci/master) |
+
+### Build Result
+- **Status:** ✅ OK
+- **Board:** sandbox
+- **Output:** `/tmp/pickman`
+
+### Fix-ups Made
+- None required - conflicts were resolved by keeping the existing HEAD versions which already contained the equivalent or better changes.
+
+### Branch Status
+- Branch `cherry-91bc909d317` is ready for pushing
+- 2 new commits ahead of `ci/master`
+- 3 commits were skipped (already present in ci/master)
+
+---
+

arch/arm/dts/bcm47622.dtsi

@@ -1,126 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 Broadcom Ltd.
- */
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
-	compatible = "brcm,bcm47622", "brcm,bcmbca";
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	interrupt-parent = <&gic>;
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		CA7_0: cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x0>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		CA7_1: cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x1>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-		CA7_2: cpu@2 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x2>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-		CA7_3: cpu@3 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x3>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-		L2_0: l2-cache0 {
-			compatible = "cache";
-		};
-	};
-
-	timer {
-		compatible = "arm,armv7-timer";
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
-		arm,cpu-registers-not-fw-configured;
-	};
-
-	pmu: pmu {
-		compatible = "arm,cortex-a7-pmu";
-		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&CA7_0>, <&CA7_1>,
-			<&CA7_2>, <&CA7_3>;
-	};
-
-	clocks: clocks {
-		periph_clk: periph-clk {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <200000000>;
-		};
-		uart_clk: uart-clk {
-			compatible = "fixed-factor-clock";
-			#clock-cells = <0>;
-			clocks = <&periph_clk>;
-			clock-div = <4>;
-			clock-mult = <1>;
-		};
-	};
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-		cpu_off = <1>;
-		cpu_on = <2>;
-	};
-
-	axi@81000000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0x81000000 0x818000>;
-
-		gic: interrupt-controller@1000 {
-			compatible = "arm,cortex-a7-gic";
-			#interrupt-cells = <3>;
-			#address-cells = <0>;
-			interrupt-controller;
-			reg = <0x1000 0x1000>,
-				<0x2000 0x2000>;
-		};
-	};
-
-	bus@ff800000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0xff800000 0x800000>;
-
-		uart0: serial@12000 {
-			compatible = "arm,pl011", "arm,primecell";
-			reg = <0x12000 0x1000>;
-			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&uart_clk>, <&uart_clk>;
-			clock-names = "uartclk", "apb_pclk";
-			status = "disabled";
-		};
-	};
-};

arch/arm/dts/bcm4912.dtsi

@@ -1,128 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 Broadcom Ltd.
- */
-
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-/ {
-	compatible = "brcm,bcm4912", "brcm,bcmbca";
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	interrupt-parent = <&gic>;
-
-	cpus {
-		#address-cells = <2>;
-		#size-cells = <0>;
-
-		B53_0: cpu@0 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x0>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		B53_1: cpu@1 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x1>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		B53_2: cpu@2 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x2>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		B53_3: cpu@3 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x3>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		L2_0: l2-cache0 {
-			compatible = "cache";
-		};
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
-	};
-
-	pmu: pmu {
-		compatible = "arm,cortex-a53-pmu";
-		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&B53_0>, <&B53_1>,
-			<&B53_2>, <&B53_3>;
-	};
-
-	clocks: clocks {
-		periph_clk: periph-clk {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <200000000>;
-		};
-		uart_clk: uart-clk {
-			compatible = "fixed-factor-clock";
-			#clock-cells = <0>;
-			clocks = <&periph_clk>;
-			clock-div = <4>;
-			clock-mult = <1>;
-		};
-	};
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	axi@81000000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x0 0x0 0x81000000 0x8000>;
-
-		gic: interrupt-controller@1000 {
-			compatible = "arm,gic-400";
-			#interrupt-cells = <3>;
-			interrupt-controller;
-			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-			reg = <0x1000 0x1000>,
-				<0x2000 0x2000>,
-				<0x4000 0x2000>,
-				<0x6000 0x2000>;
-		};
-	};
-
-	bus@ff800000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x0 0x0 0xff800000 0x800000>;
-
-		uart0: serial@12000 {
-			compatible = "arm,pl011", "arm,primecell";
-			reg = <0x12000 0x1000>;
-			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&uart_clk>, <&uart_clk>;
-			clock-names = "uartclk", "apb_pclk";
-			status = "disabled";
-		};
-	};
-};

arch/arm/dts/bcm63146.dtsi

@@ -1,110 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 Broadcom Ltd.
- */
-
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-/ {
-	compatible = "brcm,bcm63146", "brcm,bcmbca";
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	interrupt-parent = <&gic>;
-
-	cpus {
-		#address-cells = <2>;
-		#size-cells = <0>;
-
-		B53_0: cpu@0 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x0>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		B53_1: cpu@1 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x1>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		L2_0: l2-cache0 {
-			compatible = "cache";
-		};
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
-	};
-
-	pmu: pmu {
-		compatible = "arm,cortex-a53-pmu";
-		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&B53_0>, <&B53_1>;
-	};
-
-	clocks: clocks {
-		periph_clk: periph-clk {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <200000000>;
-		};
-		uart_clk: uart-clk {
-			compatible = "fixed-factor-clock";
-			#clock-cells = <0>;
-			clocks = <&periph_clk>;
-			clock-div = <4>;
-			clock-mult = <1>;
-		};
-	};
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	axi@81000000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x0 0x0 0x81000000 0x8000>;
-
-		gic: interrupt-controller@1000 {
-			compatible = "arm,gic-400";
-			#interrupt-cells = <3>;
-			interrupt-controller;
-			reg = <0x1000 0x1000>,
-				<0x2000 0x2000>,
-				<0x4000 0x2000>,
-				<0x6000 0x2000>;
-			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
-					IRQ_TYPE_LEVEL_HIGH)>;
-		};
-	};
-
-	bus@ff800000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x0 0x0 0xff800000 0x800000>;
-
-		uart0: serial@12000 {
-			compatible = "arm,pl011", "arm,primecell";
-			reg = <0x12000 0x1000>;
-			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&uart_clk>, <&uart_clk>;
-			clock-names = "uartclk", "apb_pclk";
-			status = "disabled";
-		};
-	};
-};

arch/arm/dts/bcm63158.dtsi

@@ -1,278 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com>
- * Copyright 2022 Broadcom Ltd.
- */
-
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-/ {
-	compatible = "brcm,bcm63158", "brcm,bcmbca";
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	interrupt-parent = <&gic>;
-
-	cpus {
-		#address-cells = <2>;
-		#size-cells = <0>;
-
-		B53_0: cpu@0 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x0>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		B53_1: cpu@1 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x1>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		B53_2: cpu@2 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x2>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		B53_3: cpu@3 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x3>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		L2_0: l2-cache0 {
-			compatible = "cache";
-		};
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
-	};
-
-	pmu: pmu {
-		compatible = "arm,cortex-a53-pmu";
-		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&B53_0>, <&B53_1>,
-			<&B53_2>, <&B53_3>;
-	};
-
-	clocks {
-		bootph-all;
-		periph_clk: periph-clk {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <200000000>;
-		};
-
-		hsspi_pll: hsspi-pll {
-			compatible = "fixed-factor-clock";
-			#clock-cells = <0>;
-			clocks = <&periph_clk>;
-			clock-mult = <2>;
-			clock-div = <1>;
-		};
-
-		uart_clk: uart-clk {
-			compatible = "fixed-factor-clock";
-			#clock-cells = <0>;
-			clocks = <&periph_clk>;
-			clock-div = <4>;
-			clock-mult = <1>;
-		};
-
-		wdt_clk: wdt-clk {
-			compatible = "fixed-factor-clock";
-			#clock-cells = <0>;
-			clocks = <&periph_clk>;
-			clock-div = <4>;
-			clock-mult = <1>;
-		};
-	};
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	axi@81000000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x0 0x0 0x81000000 0x8000>;
-
-		gic: interrupt-controller@1000 {
-			compatible = "arm,gic-400";
-			#interrupt-cells = <3>;
-			interrupt-controller;
-			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-			reg = <0x1000 0x1000>,
-				<0x2000 0x2000>,
-				<0x4000 0x2000>,
-				<0x6000 0x2000>;
-		};
-	};
-
-	bus@ff800000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x0 0x0 0xff800000 0x800000>;
-		bootph-all;
-
-		uart0: serial@12000 {
-			compatible = "arm,pl011", "arm,primecell";
-			reg = <0x12000 0x1000>;
-			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&uart_clk>, <&uart_clk>;
-			clock-names = "uartclk", "apb_pclk";
-			status = "disabled";
-		};
-
-		leds: led-controller@800 {
-			compatible = "brcm,bcm6858-leds";
-			reg = <0x800 0xe4>;
-
-			status = "disabled";
-		};
-
-		wdt1: watchdog@480 {
-			compatible = "brcm,bcm6345-wdt";
-			reg = <0x480 0x14>;
-			clocks = <&wdt_clk>;
-		};
-
-		wdt2: watchdog@4c0 {
-			compatible = "brcm,bcm6345-wdt";
-			reg = <0x4c0 0x14>;
-			clocks = <&wdt_clk>;
-		};
-
-		wdt-reboot {
-			compatible = "wdt-reboot";
-			wdt = <&wdt1>;
-		};
-
-		gpio0: gpio-controller@500 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x500 0x4>,
-			      <0x520 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio1: gpio-controller@504 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x504 0x4>,
-			      <0x524 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio2: gpio-controller@508 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x508 0x4>,
-			      <0x528 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio3: gpio-controller@50c {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x50c 0x4>,
-			      <0x52c 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio4: gpio-controller@510 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x510 0x4>,
-			      <0x530 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio5: gpio-controller@514 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x514 0x4>,
-			      <0x534 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio6: gpio-controller@518 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x518 0x4>,
-			      <0x538 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio7: gpio-controller@51c {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x51c 0x4>,
-			      <0x53c 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		hsspi: spi-controller@1000 {
-			compatible = "brcm,bcm6328-hsspi";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x1000 0x600>;
-			clocks = <&hsspi_pll>, <&hsspi_pll>;
-			clock-names = "hsspi", "pll";
-			spi-max-frequency = <100000000>;
-			num-cs = <8>;
-
-			status = "disabled";
-		};
-
-		nand: nand-controller@1800 {
-			compatible = "brcm,nand-bcm63158",
-				     "brcm,brcmnand-v5.0",
-				     "brcm,brcmnand";
-			reg-names = "nand", "nand-int-base", "nand-cache";
-			reg = <0x1800 0x180>,
-			      <0x2000 0x10>,
-			      <0x1c00 0x200>;
-			parameter-page-big-endian = <0>;
-
-			status = "disabled";
-		};
-	};
-};

arch/arm/dts/bcm63178.dtsi

@@ -1,120 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 Broadcom Ltd.
- */
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
-	compatible = "brcm,bcm63178", "brcm,bcmbca";
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	interrupt-parent = <&gic>;
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		CA7_0: cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x0>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		CA7_1: cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x1>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		CA7_2: cpu@2 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x2>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		L2_0: l2-cache0 {
-			compatible = "cache";
-		};
-	};
-
-	timer {
-		compatible = "arm,armv7-timer";
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>;
-		arm,cpu-registers-not-fw-configured;
-	};
-
-	pmu: pmu {
-		compatible = "arm,cortex-a7-pmu";
-		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&CA7_0>, <&CA7_1>,
-			<&CA7_2>;
-	};
-
-	clocks: clocks {
-		periph_clk: periph-clk {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <200000000>;
-		};
-		uart_clk: uart-clk {
-			compatible = "fixed-factor-clock";
-			#clock-cells = <0>;
-			clocks = <&periph_clk>;
-			clock-div = <4>;
-			clock-mult = <1>;
-		};
-	};
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	axi@81000000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0x81000000 0x8000>;
-
-		gic: interrupt-controller@1000 {
-			compatible = "arm,cortex-a7-gic";
-			#interrupt-cells = <3>;
-			interrupt-controller;
-			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>;
-			reg = <0x1000 0x1000>,
-				<0x2000 0x2000>,
-				<0x4000 0x2000>,
-				<0x6000 0x2000>;
-		};
-	};
-
-	bus@ff800000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0xff800000 0x800000>;
-
-		uart0: serial@12000 {
-			compatible = "arm,pl011", "arm,primecell";
-			reg = <0x12000 0x1000>;
-			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&uart_clk>, <&uart_clk>;
-			clock-names = "uartclk", "apb_pclk";
-			status = "disabled";
-		};
-	};
-};

arch/arm/dts/bcm6756.dtsi

@@ -1,130 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 Broadcom Ltd.
- */
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
-	compatible = "brcm,bcm6756", "brcm,bcmbca";
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	interrupt-parent = <&gic>;
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		CA7_0: cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x0>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		CA7_1: cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x1>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		CA7_2: cpu@2 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x2>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		CA7_3: cpu@3 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x3>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		L2_0: l2-cache0 {
-			compatible = "cache";
-		};
-	};
-
-	timer {
-		compatible = "arm,armv7-timer";
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
-		arm,cpu-registers-not-fw-configured;
-	};
-
-	pmu: pmu {
-		compatible = "arm,cortex-a7-pmu";
-		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&CA7_0>, <&CA7_1>,
-			<&CA7_2>, <&CA7_3>;
-	};
-
-	clocks: clocks {
-		periph_clk: periph-clk {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <200000000>;
-		};
-
-		uart_clk: uart-clk {
-			compatible = "fixed-factor-clock";
-			#clock-cells = <0>;
-			clocks = <&periph_clk>;
-			clock-div = <4>;
-			clock-mult = <1>;
-		};
-	};
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	axi@81000000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0x81000000 0x8000>;
-
-		gic: interrupt-controller@1000 {
-			compatible = "arm,cortex-a7-gic";
-			#interrupt-cells = <3>;
-			interrupt-controller;
-			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-			reg = <0x1000 0x1000>,
-				<0x2000 0x2000>,
-				<0x4000 0x2000>,
-				<0x6000 0x2000>;
-		};
-	};
-
-	bus@ff800000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0xff800000 0x800000>;
-
-		uart0: serial@12000 {
-			compatible = "arm,pl011", "arm,primecell";
-			reg = <0x12000 0x1000>;
-			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&uart_clk>, <&uart_clk>;
-			clock-names = "uartclk", "apb_pclk";
-			status = "disabled";
-		};
-	};
-};

arch/arm/dts/bcm6813.dtsi

@@ -1,128 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 Broadcom Ltd.
- */
-
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-/ {
-	compatible = "brcm,bcm6813", "brcm,bcmbca";
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	interrupt-parent = <&gic>;
-
-	cpus {
-		#address-cells = <2>;
-		#size-cells = <0>;
-
-		B53_0: cpu@0 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x0>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		B53_1: cpu@1 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x1>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		B53_2: cpu@2 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x2>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		B53_3: cpu@3 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x3>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		L2_0: l2-cache0 {
-			compatible = "cache";
-		};
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
-	};
-
-	pmu: pmu {
-		compatible = "arm,cortex-a53-pmu";
-		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&B53_0>, <&B53_1>,
-			<&B53_2>, <&B53_3>;
-	};
-
-	clocks: clocks {
-		periph_clk: periph-clk {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <200000000>;
-		};
-		uart_clk: uart-clk {
-			compatible = "fixed-factor-clock";
-			#clock-cells = <0>;
-			clocks = <&periph_clk>;
-			clock-div = <4>;
-			clock-mult = <1>;
-		};
-	};
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	axi@81000000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x0 0x0 0x81000000 0x8000>;
-
-		gic: interrupt-controller@1000 {
-			compatible = "arm,gic-400";
-			#interrupt-cells = <3>;
-			interrupt-controller;
-			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-			reg = <0x1000 0x1000>,
-				<0x2000 0x2000>,
-				<0x4000 0x2000>,
-				<0x6000 0x2000>;
-		};
-	};
-
-	bus@ff800000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x0 0x0 0xff800000 0x800000>;
-
-		uart0: serial@12000 {
-			compatible = "arm,pl011", "arm,primecell";
-			reg = <0x12000 0x1000>;
-			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&uart_clk>, <&uart_clk>;
-			clock-names = "uartclk", "apb_pclk";
-			status = "disabled";
-		};
-	};
-};

arch/arm/dts/bcm6855.dtsi

@@ -1,257 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2022 Philippe Reynes <philippe.reynes@softathome.com>
- * Copyright 2022 Broadcom Ltd.
- */
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
-	compatible = "brcm,bcm6855", "brcm,bcmbca";
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	interrupt-parent = <&gic>;
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		CA7_0: cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x0>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		CA7_1: cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x1>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		CA7_2: cpu@2 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x2>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		L2_0: l2-cache0 {
-			compatible = "cache";
-		};
-	};
-
-	timer {
-		compatible = "arm,armv7-timer";
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>;
-		arm,cpu-registers-not-fw-configured;
-	};
-
-	pmu: pmu {
-		compatible = "arm,cortex-a7-pmu";
-		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&CA7_0>, <&CA7_1>, <&CA7_2>;
-	};
-
-	clocks: clocks {
-		bootph-all;
-
-		periph_clk: periph-clk {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <200000000>;
-		};
-
-		uart_clk: uart-clk {
-			compatible = "fixed-factor-clock";
-			#clock-cells = <0>;
-			clocks = <&periph_clk>;
-			clock-div = <4>;
-			clock-mult = <1>;
-		};
-
-		hsspi_pll: hsspi-pll {
-			compatible = "fixed-factor-clock";
-			#clock-cells = <0>;
-			clocks = <&periph_clk>;
-			clock-mult = <2>;
-			clock-div = <1>;
-		};
-
-		wdt_clk: wdt-clk {
-			compatible = "fixed-factor-clock";
-			#clock-cells = <0>;
-			clocks = <&periph_clk>;
-			clock-div = <4>;
-			clock-mult = <1>;
-		};
-	};
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	axi@81000000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0x81000000 0x8000>;
-
-		gic: interrupt-controller@1000 {
-			compatible = "arm,cortex-a7-gic";
-			#interrupt-cells = <3>;
-			interrupt-controller;
-			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>;
-			reg = <0x1000 0x1000>,
-				<0x2000 0x2000>,
-				<0x4000 0x2000>,
-				<0x6000 0x2000>;
-		};
-	};
-
-	bus@ff800000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0xff800000 0x800000>;
-		bootph-all;
-
-		uart0: serial@12000 {
-			compatible = "arm,pl011", "arm,primecell";
-			reg = <0x12000 0x1000>;
-			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&uart_clk>, <&uart_clk>;
-			clock-names = "uartclk", "apb_pclk";
-			status = "disabled";
-		};
-
-		wdt1: watchdog@480 {
-			compatible = "brcm,bcm6345-wdt";
-			reg = <0x480 0x14>;
-			clocks = <&wdt_clk>;
-		};
-
-		wdt2: watchdog@4c0 {
-			compatible = "brcm,bcm6345-wdt";
-			reg = <0x4c0 0x14>;
-			clocks = <&wdt_clk>;
-		};
-
-		wdt-reboot {
-			compatible = "wdt-reboot";
-			wdt = <&wdt1>;
-		};
-
-		gpio0: gpio-controller@500 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x500 0x4>,
-			      <0x520 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio1: gpio-controller@504 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x504 0x4>,
-			      <0x524 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio2: gpio-controller@508 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x508 0x4>,
-			      <0x528 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio3: gpio-controller@50c {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x50c 0x4>,
-			      <0x52c 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio4: gpio-controller@510 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x510 0x4>,
-			      <0x530 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio5: gpio-controller@514 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x514 0x4>,
-			      <0x534 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio6: gpio-controller@518 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x518 0x4>,
-			      <0x538 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio7: gpio-controller@51c {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x51c 0x4>,
-			      <0x53c 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		nand: nand-controller@1800 {
-			compatible = "brcm,nand-bcm6753",
-				     "brcm,brcmnand-v5.0",
-				     "brcm,brcmnand";
-			reg-names = "nand", "nand-int-base", "nand-cache";
-			reg = <0x1800 0x180>,
-			      <0x2000 0x10>,
-			      <0x1c00 0x200>;
-			parameter-page-big-endian = <0>;
-
-			status = "disabled";
-		};
-
-		leds: led-controller@3000 {
-			compatible = "brcm,bcm6753-leds";
-			reg = <0x3000 0x3480>;
-
-			status = "disabled";
-		};
-	};
-};

arch/arm/dts/bcm6856.dtsi

@@ -1,253 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2020 Philippe Reynes <philippe.reynes@softathome.com>
- * Copyright 2022 Broadcom Ltd.
- */
-
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-/ {
-	compatible = "brcm,bcm6856", "brcm,bcmbca";
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	interrupt-parent = <&gic>;
-
-	cpus {
-		#address-cells = <2>;
-		#size-cells = <0>;
-
-		B53_0: cpu@0 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x0>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		B53_1: cpu@1 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x1>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		L2_0: l2-cache0 {
-			compatible = "cache";
-		};
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
-	};
-
-	pmu: pmu {
-		compatible = "arm,cortex-a53-pmu";
-		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&B53_0>, <&B53_1>;
-	};
-
-	clocks: clocks {
-		bootph-all;
-
-		periph_clk:periph-clk {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <200000000>;
-		};
-
-		hsspi_pll: hsspi-pll {
-			compatible = "fixed-factor-clock";
-			#clock-cells = <0>;
-			clocks = <&periph_clk>;
-			clock-mult = <2>;
-			clock-div = <1>;
-		};
-
-		wdt_clk: wdt-clk {
-			compatible = "fixed-factor-clock";
-			#clock-cells = <0>;
-			clocks = <&periph_clk>;
-			clock-div = <4>;
-			clock-mult = <1>;
-		};
-	};
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	axi@81000000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x0 0x0 0x81000000 0x8000>;
-
-		gic: interrupt-controller@1000 {
-			compatible = "arm,gic-400";
-			#interrupt-cells = <3>;
-			interrupt-controller;
-			reg = <0x1000 0x1000>, /* GICD */
-				<0x2000 0x2000>, /* GICC */
-				<0x4000 0x2000>, /* GICH */
-				<0x6000 0x2000>; /* GICV */
-			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
-					IRQ_TYPE_LEVEL_HIGH)>;
-		};
-	};
-
-	bus@ff800000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x0 0x0 0xff800000 0x800000>;
-		bootph-all;
-
-		uart0: serial@640 {
-			compatible = "brcm,bcm6345-uart";
-			reg = <0x640 0x18>;
-			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&periph_clk>;
-			clock-names = "refclk";
-			status = "disabled";
-		};
-
-		wdt1: watchdog@480 {
-			compatible = "brcm,bcm6345-wdt";
-			reg = <0x480 0x14>;
-			clocks = <&wdt_clk>;
-		};
-
-		wdt2: watchdog@4c0 {
-			compatible = "brcm,bcm6345-wdt";
-			reg = <0x4c0 0x14>;
-			clocks = <&wdt_clk>;
-		};
-
-		wdt-reboot {
-			compatible = "wdt-reboot";
-			wdt = <&wdt1>;
-		};
-
-		leds: led-controller@800 {
-			compatible = "brcm,bcm6858-leds";
-			reg = <0x800 0xe4>;
-
-			status = "disabled";
-		};
-
-		gpio0: gpio-controller@500 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x500 0x4>,
-			      <0x520 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio1: gpio-controller@504 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x504 0x4>,
-			      <0x524 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio2: gpio-controller@508 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x508 0x4>,
-			      <0x528 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio3: gpio-controller@50c {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x50c 0x4>,
-			      <0x52c 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio4: gpio-controller@510 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x510 0x4>,
-			      <0x530 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio5: gpio-controller@514 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x514 0x4>,
-			      <0x534 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio6: gpio-controller@518 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x518 0x4>,
-			      <0x538 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio7: gpio-controller@51c {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x51c 0x4>,
-			      <0x53c 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		hsspi: spi-controller@1000 {
-			compatible = "brcm,bcm6328-hsspi";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x1000 0x600>;
-			clocks = <&hsspi_pll>, <&hsspi_pll>;
-			clock-names = "hsspi", "pll";
-			spi-max-frequency = <100000000>;
-			num-cs = <8>;
-
-			status = "disabled";
-		};
-
-		nand: nand-controller@1800 {
-			compatible = "brcm,nand-bcm68360",
-				     "brcm,brcmnand-v5.0",
-				     "brcm,brcmnand";
-			reg-names = "nand", "nand-int-base", "nand-cache";
-			reg = <0x1800 0x180>,
-			      <0x2000 0x10>,
-			      <0x1c00 0x200>;
-			parameter-page-big-endian = <0>;
-
-			status = "disabled";
-		};
-	};
-};

arch/arm/dts/bcm6858.dtsi

@@ -1,272 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
- * Copyright 2022 Broadcom Ltd.
- */
-
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-/ {
-	compatible = "brcm,bcm6858", "brcm,bcmbca";
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	interrupt-parent = <&gic>;
-
-	cpus {
-		#address-cells = <2>;
-		#size-cells = <0>;
-
-		B53_0: cpu@0 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x0>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		B53_1: cpu@1 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x1>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		B53_2: cpu@2 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x2>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		B53_3: cpu@3 {
-			compatible = "brcm,brahma-b53";
-			device_type = "cpu";
-			reg = <0x0 0x3>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		L2_0: l2-cache0 {
-			compatible = "cache";
-		};
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
-	};
-
-	pmu: pmu {
-		compatible = "arm,armv8-pmuv3";
-		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&B53_0>, <&B53_1>,
-			<&B53_2>, <&B53_3>;
-	};
-
-	clocks {
-		bootph-all;
-
-		periph_clk: periph_clk {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <200000000>;
-		};
-
-		hsspi_pll: hsspi-pll {
-			compatible = "fixed-factor-clock";
-			#clock-cells = <0>;
-			clocks = <&periph_clk>;
-			clock-mult = <2>;
-			clock-div = <1>;
-		};
-
-		wdt_clk: wdt-clk {
-			compatible = "fixed-factor-clock";
-			#clock-cells = <0>;
-			clocks = <&periph_clk>;
-			clock-div = <4>;
-			clock-mult = <1>;
-		};
-	};
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	axi@81000000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x0 0x0 0x81000000 0x8000>;
-
-		gic: interrupt-controller@1000 {
-			compatible = "arm,gic-400";
-			#interrupt-cells = <3>;
-			interrupt-controller;
-			reg = <0x1000 0x1000>, /* GICD */
-				<0x2000 0x2000>, /* GICC */
-				<0x4000 0x2000>, /* GICH */
-				<0x6000 0x2000>; /* GICV */
-			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
-					IRQ_TYPE_LEVEL_HIGH)>;
-		};
-	};
-
-	bus@ff800000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x0 0x0 0xff800000 0x800000>;
-		bootph-all;
-
-		uart0: serial@640 {
-			compatible = "brcm,bcm6345-uart";
-			reg = <0x640 0x18>;
-			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&periph_clk>;
-			clock-names = "refclk";
-			status = "disabled";
-		};
-
-		leds: led-controller@800 {
-			compatible = "brcm,bcm6858-leds";
-			reg = <0x800 0xe4>;
-
-			status = "disabled";
-		};
-
-		wdt1: watchdog@2780 {
-			compatible = "brcm,bcm6345-wdt";
-			reg = <0x2780 0x14>;
-			clocks = <&wdt_clk>;
-		};
-
-		wdt2: watchdog@27c0 {
-			compatible = "brcm,bcm6345-wdt";
-			reg = <0x27c0 0x14>;
-			clocks = <&wdt_clk>;
-		};
-
-		wdt-reboot {
-			compatible = "wdt-reboot";
-			wdt = <&wdt1>;
-		};
-
-		gpio0: gpio-controller@500 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x500 0x4>,
-			      <0x520 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio1: gpio-controller@504 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x504 0x4>,
-			      <0x524 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio2: gpio-controller@508 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x508 0x4>,
-			      <0x528 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio3: gpio-controller@50c {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x50c 0x4>,
-			      <0x52c 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio4: gpio-controller@510 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x510 0x4>,
-			      <0x530 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio5: gpio-controller@514 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x514 0x4>,
-			      <0x534 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio6: gpio-controller@518 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x518 0x4>,
-			      <0x538 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		gpio7: gpio-controller@51c {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x51c 0x4>,
-			      <0x53c 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
-
-		hsspi: spi-controller@1000 {
-			compatible = "brcm,bcm6328-hsspi";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x1000 0x600>;
-			clocks = <&hsspi_pll>, <&hsspi_pll>;
-			clock-names = "hsspi", "pll";
-			spi-max-frequency = <100000000>;
-			num-cs = <8>;
-
-			status = "disabled";
-		};
-
-		nand: nand-controller@1800 {
-			compatible = "brcm,nand-bcm6858",
-				     "brcm,brcmnand-v5.0",
-				     "brcm,brcmnand";
-			reg-names = "nand", "nand-int-base", "nand-cache";
-			reg = <0x1800 0x180>,
-			      <0x2000 0x10>,
-			      <0x1c00 0x200>;
-			parameter-page-big-endian = <0>;
-
-			status = "disabled";
-		};
-	};
-};

arch/arm/dts/bcm6878.dtsi

@@ -1,111 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 Broadcom Ltd.
- */
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
-	compatible = "brcm,bcm6878", "brcm,bcmbca";
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	interrupt-parent = <&gic>;
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		CA7_0: cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x0>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		CA7_1: cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x1>;
-			next-level-cache = <&L2_0>;
-			enable-method = "psci";
-		};
-
-		L2_0: l2-cache0 {
-			compatible = "cache";
-		};
-	};
-
-	timer {
-		compatible = "arm,armv7-timer";
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
-		arm,cpu-registers-not-fw-configured;
-	};
-
-	pmu: pmu {
-		compatible = "arm,cortex-a7-pmu";
-		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&CA7_0>, <&CA7_1>;
-	};
-
-	clocks: clocks {
-		periph_clk: periph-clk {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <200000000>;
-		};
-		uart_clk: uart-clk {
-			compatible = "fixed-factor-clock";
-			#clock-cells = <0>;
-			clocks = <&periph_clk>;
-			clock-div = <4>;
-			clock-mult = <1>;
-		};
-	};
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	axi@81000000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0x81000000 0x8000>;
-
-		gic: interrupt-controller@1000 {
-			compatible = "arm,cortex-a7-gic";
-			#interrupt-cells = <3>;
-			interrupt-controller;
-			reg = <0x1000 0x1000>,
-				<0x2000 0x2000>,
-				<0x4000 0x2000>,
-				<0x6000 0x2000>;
-			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
-					IRQ_TYPE_LEVEL_HIGH)>;
-		};
-	};
-
-	bus@ff800000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0xff800000 0x800000>;
-
-		uart0: serial@12000 {
-			compatible = "arm,pl011", "arm,primecell";
-			reg = <0x12000 0x1000>;
-			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&uart_clk>, <&uart_clk>;
-			clock-names = "uartclk", "apb_pclk";
-			status = "disabled";
-		};
-	};
-};

arch/arm/dts/bcm947622.dts

@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2019 Broadcom Ltd.
- */
-
-/dts-v1/;
-
-#include "bcm47622.dtsi"
-
-/ {
-	model = "Broadcom BCM947622 Reference Board";
-	compatible = "brcm,bcm947622", "brcm,bcm47622", "brcm,bcmbca";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x08000000>;
-	};
-};
-
-&uart0 {
-	status = "okay";
-};

arch/arm/dts/bcm94912.dts

@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 Broadcom Ltd.
- */
-
-/dts-v1/;
-
-#include "bcm4912.dtsi"
-
-/ {
-	model = "Broadcom BCM94912 Reference Board";
-	compatible = "brcm,bcm94912", "brcm,bcm4912", "brcm,bcmbca";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x0 0x0 0x08000000>;
-	};
-};
-
-&uart0 {
-	status = "okay";
-};

arch/arm/dts/bcm963146.dts

@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 Broadcom Ltd.
- */
-
-/dts-v1/;
-
-#include "bcm63146.dtsi"
-
-/ {
-	model = "Broadcom BCM963146 Reference Board";
-	compatible = "brcm,bcm963146", "brcm,bcm63146", "brcm,bcmbca";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x0 0x0 0x08000000>;
-	};
-};
-
-&uart0 {
-	status = "okay";
-};

arch/arm/dts/bcm963158.dts

@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 Broadcom Ltd.
- */
-
-/dts-v1/;
-
-#include "bcm63158.dtsi"
-
-/ {
-	model = "Broadcom BCM963158 Reference Board";
-	compatible = "brcm,bcm963158", "brcm,bcm63158", "brcm,bcmbca";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x0 0x0 0x08000000>;
-	};
-};
-
-&uart0 {
-	status = "okay";
-};

arch/arm/dts/bcm963178.dts

@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2019 Broadcom Ltd.
- */
-
-/dts-v1/;
-
-#include "bcm63178.dtsi"
-
-/ {
-	model = "Broadcom BCM963178 Reference Board";
-	compatible = "brcm,bcm963178", "brcm,bcm63178", "brcm,bcmbca";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x08000000>;
-	};
-};
-
-&uart0 {
-	status = "okay";
-};

arch/arm/dts/bcm96756.dts

@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2019 Broadcom Ltd.
- */
-
-/dts-v1/;
-
-#include "bcm6756.dtsi"
-
-/ {
-	model = "Broadcom BCM96756 Reference Board";
-	compatible = "brcm,bcm96756", "brcm,bcm6756", "brcm,bcmbca";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x08000000>;
-	};
-};
-
-&uart0 {
-	status = "okay";
-};

arch/arm/dts/bcm96813.dts

@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 Broadcom Ltd.
- */
-
-/dts-v1/;
-
-#include "bcm6813.dtsi"
-
-/ {
-	model = "Broadcom BCM96813 Reference Board";
-	compatible = "brcm,bcm96813", "brcm,bcm6813", "brcm,bcmbca";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x0 0x0 0x08000000>;
-	};
-};
-
-&uart0 {
-	status = "okay";
-};

arch/arm/dts/bcm96855.dts

@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 Broadcom Ltd.
- */
-
-/dts-v1/;
-
-#include "bcm6855.dtsi"
-
-/ {
-	model = "Broadcom BCM96855 Reference Board";
-	compatible = "brcm,bcm96855", "brcm,bcm6855", "brcm,bcmbca";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x08000000>;
-	};
-};
-
-&uart0 {
-	status = "okay";
-};

arch/arm/dts/bcm96856.dts

@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 Broadcom Ltd.
- */
-
-/dts-v1/;
-
-#include "bcm6856.dtsi"
-
-/ {
-	model = "Broadcom BCM96856 Reference Board";
-	compatible = "brcm,bcm96856", "brcm,bcm6856", "brcm,bcmbca";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x0 0x0 0x08000000>;
-	};
-};
-
-&uart0 {
-	status = "okay";
-};

arch/arm/dts/bcm96858.dts

@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 Broadcom Ltd.
- */
-
-/dts-v1/;
-
-#include "bcm6858.dtsi"
-
-/ {
-	model = "Broadcom BCM96858 Reference Board";
-	compatible = "brcm,bcm96858", "brcm,bcm6858", "brcm,bcmbca";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x0 0x0 0x08000000>;
-	};
-};
-
-&uart0 {
-	status = "okay";
-};

arch/arm/dts/bcm96878.dts

@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2019 Broadcom Ltd.
- */
-
-/dts-v1/;
-
-#include "bcm6878.dtsi"
-
-/ {
-	model = "Broadcom BCM96878 Reference Board";
-	compatible = "brcm,bcm96878", "brcm,bcm6878", "brcm,bcmbca";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x08000000>;
-	};
-};
-
-&uart0 {
-	status = "okay";
-};

arch/arm/mach-bcmbca/bcm47622/Kconfig

@@ -8,6 +8,7 @@ if BCM47622
 config TARGET_BCM947622
 	bool "Broadcom 47622 Reference Board"
 	depends on ARCH_BCMBCA
+	imply OF_UPSTREAM
 
 config SYS_SOC
 	default "bcm47622"

arch/arm/mach-bcmbca/bcm4912/Kconfig

@@ -8,6 +8,7 @@ if BCM4912
 config TARGET_BCM94912
 	bool "Broadcom 4912 Reference Board"
 	depends on ARCH_BCMBCA
+	imply OF_UPSTREAM
 
 config SYS_SOC
 	default "bcm4912"

arch/arm/mach-bcmbca/bcm63146/Kconfig

@@ -8,6 +8,7 @@ if BCM63146
 config TARGET_BCM963146
 	bool "Broadcom 63146 Reference Board"
 	depends on ARCH_BCMBCA
+	imply OF_UPSTREAM
 
 config SYS_SOC
 	default "bcm63146"

arch/arm/mach-bcmbca/bcm63158/Kconfig

@@ -8,6 +8,7 @@ if BCM63158
 config TARGET_BCM963158
 	bool "Broadcom 63158 Reference Board"
 	depends on ARCH_BCMBCA
+	imply OF_UPSTREAM
 
 config SYS_SOC
 	default "bcm63158"

arch/arm/mach-bcmbca/bcm63178/Kconfig

@@ -8,6 +8,7 @@ if BCM63178
 config TARGET_BCM963178
 	bool "Broadcom 63178 Reference Board"
 	depends on ARCH_BCMBCA
+	imply OF_UPSTREAM
 
 config SYS_SOC
 	default "bcm63178"

arch/arm/mach-bcmbca/bcm6756/Kconfig

@@ -8,6 +8,7 @@ if BCM6756
 config TARGET_BCM96756
 	bool "Broadcom 6756 Reference Board"
 	depends on ARCH_BCMBCA
+	imply OF_UPSTREAM
 
 config SYS_SOC
 	default "bcm6756"

arch/arm/mach-bcmbca/bcm6813/Kconfig

@@ -8,6 +8,7 @@ if BCM6813
 config TARGET_BCM96813
 	bool "Broadcom 6813 Reference Board"
 	depends on ARCH_BCMBCA
+	imply OF_UPSTREAM
 
 config SYS_SOC
 	default "bcm6813"

arch/arm/mach-bcmbca/bcm6855/Kconfig

@@ -8,6 +8,7 @@ if BCM6855
 config TARGET_BCM96855
 	bool "Broadcom 6855 Reference Board"
 	depends on ARCH_BCMBCA
+	imply OF_UPSTREAM
 
 config SYS_SOC
 	default "bcm6855"

arch/arm/mach-bcmbca/bcm6856/Kconfig

@@ -8,6 +8,7 @@ if BCM6856
 config TARGET_BCM96856
 	bool "Broadcom 6856 Reference Board"
 	depends on ARCH_BCMBCA
+	imply OF_UPSTREAM
 
 config SYS_SOC
 	default "bcm6856"

arch/arm/mach-bcmbca/bcm6858/Kconfig

@@ -8,6 +8,7 @@ if BCM6858
 config TARGET_BCM96858
 	bool "Broadcom 6858 Reference Board"
 	depends on ARCH_BCMBCA
+	imply OF_UPSTREAM
 
 config SYS_SOC
 	default "bcm6858"

arch/arm/mach-bcmbca/bcm6878/Kconfig

@@ -8,6 +8,7 @@ if BCM6878
 config TARGET_BCM96878
 	bool "Broadcom 6878 Reference Board"
 	depends on ARCH_BCMBCA
+	imply OF_UPSTREAM
 
 config SYS_SOC
 	default "bcm6878"

configs/bcm947622_defconfig

@@ -8,7 +8,7 @@ CONFIG_TARGET_BCM947622=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
-CONFIG_DEFAULT_DEVICE_TREE="bcm947622"
+CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcm947622"
 CONFIG_SYS_BOOTM_LEN=0x2000000
 CONFIG_SYS_LOAD_ADDR=0x01000000
 CONFIG_IDENT_STRING=" Broadcom BCM47622"
@@ -16,6 +16,15 @@ CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_NAND=y
 CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
 CONFIG_OF_EMBED=y
+CONFIG_DM=y
 CONFIG_CLK=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_NAND_BRCMNAND_BCMBCA=y

configs/bcm94912_defconfig

@@ -9,13 +9,22 @@ CONFIG_TARGET_BCM94912=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
-CONFIG_DEFAULT_DEVICE_TREE="bcm94912"
+CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcmbca/bcm94912"
 CONFIG_SYS_LOAD_ADDR=0x01000000
 CONFIG_IDENT_STRING=" Broadcom BCM4912"
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_NAND=y
 CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
 CONFIG_OF_EMBED=y
+CONFIG_DM=y
 CONFIG_CLK=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_NAND_BRCMNAND_BCMBCA=y

configs/bcm963146_defconfig

@@ -9,13 +9,22 @@ CONFIG_TARGET_BCM963146=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
-CONFIG_DEFAULT_DEVICE_TREE="bcm963146"
+CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcmbca/bcm963146"
 CONFIG_SYS_LOAD_ADDR=0x01000000
 CONFIG_IDENT_STRING=" Broadcom BCM63146"
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_NAND=y
 CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
 CONFIG_OF_EMBED=y
+CONFIG_DM=y
 CONFIG_CLK=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_NAND_BRCMNAND_BCMBCA=y

configs/bcm963158_defconfig

@@ -9,13 +9,22 @@ CONFIG_TARGET_BCM963158=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
-CONFIG_DEFAULT_DEVICE_TREE="bcm963158"
+CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcmbca/bcm963158"
 CONFIG_SYS_LOAD_ADDR=0x01000000
 CONFIG_IDENT_STRING=" Broadcom BCM63158"
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_NAND=y
 CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
 CONFIG_OF_EMBED=y
+CONFIG_DM=y
 CONFIG_CLK=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_NAND_BRCMNAND_BCMBCA=y

configs/bcm963178_defconfig

@@ -9,7 +9,7 @@ CONFIG_TARGET_BCM963178=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
-CONFIG_DEFAULT_DEVICE_TREE="bcm963178"
+CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcm963178"
 CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_SYS_LOAD_ADDR=0x01000000
 CONFIG_IDENT_STRING=" Broadcom BCM63178"
@@ -17,6 +17,15 @@ CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_NAND=y
 CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
 CONFIG_OF_EMBED=y
+CONFIG_DM=y
 CONFIG_CLK=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_NAND_BRCMNAND_BCMBCA=y

configs/bcm96756_defconfig

@@ -9,7 +9,7 @@ CONFIG_TARGET_BCM96756=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
-CONFIG_DEFAULT_DEVICE_TREE="bcm96756"
+CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcm96756"
 CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_SYS_LOAD_ADDR=0x01000000
 CONFIG_IDENT_STRING=" Broadcom BCM6756"
@@ -17,6 +17,15 @@ CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_NAND=y
 CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
 CONFIG_OF_EMBED=y
+CONFIG_DM=y
 CONFIG_CLK=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_NAND_BRCMNAND_BCMBCA=y

configs/bcm96813_defconfig

@@ -9,13 +9,22 @@ CONFIG_TARGET_BCM96813=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
-CONFIG_DEFAULT_DEVICE_TREE="bcm96813"
+CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcmbca/bcm96813"
 CONFIG_SYS_LOAD_ADDR=0x01000000
 CONFIG_IDENT_STRING=" Broadcom BCM6813"
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_NAND=y
 CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
 CONFIG_OF_EMBED=y
+CONFIG_DM=y
 CONFIG_CLK=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_NAND_BRCMNAND_BCMBCA=y

configs/bcm96855_defconfig

@@ -9,7 +9,7 @@ CONFIG_TARGET_BCM96855=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
-CONFIG_DEFAULT_DEVICE_TREE="bcm96855"
+CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcm96855"
 CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_SYS_LOAD_ADDR=0x01000000
 CONFIG_IDENT_STRING=" Broadcom BCM6855"
@@ -17,6 +17,15 @@ CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_NAND=y
 CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
 CONFIG_OF_EMBED=y
+CONFIG_DM=y
 CONFIG_CLK=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_NAND_BRCMNAND_BCMBCA=y

configs/bcm96856_defconfig

@@ -9,13 +9,22 @@ CONFIG_TARGET_BCM96856=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
-CONFIG_DEFAULT_DEVICE_TREE="bcm96856"
+CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcmbca/bcm96856"
 CONFIG_SYS_LOAD_ADDR=0x01000000
 CONFIG_IDENT_STRING=" Broadcom BCM6856"
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_NAND=y
 CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
 CONFIG_OF_EMBED=y
+CONFIG_DM=y
 CONFIG_CLK=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_NAND_BRCMNAND_BCMBCA=y

configs/bcm96858_defconfig

@@ -9,13 +9,22 @@ CONFIG_TARGET_BCM96858=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
-CONFIG_DEFAULT_DEVICE_TREE="bcm96858"
+CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcmbca/bcm96858"
 CONFIG_SYS_LOAD_ADDR=0x01000000
 CONFIG_IDENT_STRING=" Broadcom BCM6858"
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_NAND=y
 CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
 CONFIG_OF_EMBED=y
+CONFIG_DM=y
 CONFIG_CLK=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_NAND_BRCMNAND_BCMBCA=y

configs/bcm96878_defconfig

@@ -9,7 +9,7 @@ CONFIG_TARGET_BCM96878=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
-CONFIG_DEFAULT_DEVICE_TREE="bcm96878"
+CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcm96878"
 CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_SYS_LOAD_ADDR=0x01000000
 CONFIG_IDENT_STRING=" Broadcom BCM6878"
@@ -17,6 +17,15 @@ CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_NAND=y
 CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
 CONFIG_OF_EMBED=y
+CONFIG_DM=y
 CONFIG_CLK=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_NAND_BRCMNAND_BCMBCA=y

configs/sifive_unmatched_defconfig

@@ -36,6 +36,7 @@ CONFIG_DISPLAY_BOARDINFO=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_ID_EEPROM=y
 CONFIG_PCI_INIT_R=y
+CONFIG_PCI_REGION_MULTI_ENTRY=y
 CONFIG_SPL_MAX_SIZE=0x100000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_HAVE_INIT_STACK=y
@@ -43,6 +44,7 @@ CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_SPI_LOAD=y
+CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_EEPROM=y
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_PWM=y

drivers/mtd/nand/raw/Kconfig

@@ -133,36 +133,12 @@ config NAND_BRCMNAND_6368
 	help
 	  Enable support for broadcom nand driver on bcm6368.
 
-config NAND_BRCMNAND_6753
-	bool "Support Broadcom NAND controller on bcm6753"
-	depends on NAND_BRCMNAND && BCM6855
-	help
-	  Enable support for broadcom nand driver on bcm6753.
-
-config NAND_BRCMNAND_68360
-	bool "Support Broadcom NAND controller on bcm68360"
-	depends on NAND_BRCMNAND && BCM6856
-	help
-	  Enable support for broadcom nand driver on bcm68360.
-
 config NAND_BRCMNAND_6838
 	bool "Support Broadcom NAND controller on bcm6838"
 	depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838
 	help
 	  Enable support for broadcom nand driver on bcm6838.
 
-config NAND_BRCMNAND_6858
-	bool "Support Broadcom NAND controller on bcm6858"
-	depends on NAND_BRCMNAND && BCM6858
-	help
-	  Enable support for broadcom nand driver on bcm6858.
-
-config NAND_BRCMNAND_63158
-	bool "Support Broadcom NAND controller on bcm63158"
-	depends on NAND_BRCMNAND && BCM63158
-	help
-	  Enable support for broadcom nand driver on bcm63158.
-
 config NAND_BRCMNAND_IPROC
 	bool "Support Broadcom NAND controller on the iproc family"
 	depends on NAND_BRCMNAND

drivers/mtd/nand/raw/brcmnand/Makefile

@@ -1,11 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 
 obj-$(CONFIG_NAND_BRCMNAND_6368) += bcm6368_nand.o
-obj-$(CONFIG_NAND_BRCMNAND_63158) += bcm63158_nand.o
-obj-$(CONFIG_NAND_BRCMNAND_6753) += bcm6753_nand.o
-obj-$(CONFIG_NAND_BRCMNAND_68360) += bcm68360_nand.o
 obj-$(CONFIG_NAND_BRCMNAND_6838) += bcm6838_nand.o
-obj-$(CONFIG_NAND_BRCMNAND_6858) += bcm6858_nand.o
 obj-$(CONFIG_NAND_BRCMNAND_BCMBCA) += bcmbca_nand.o
 obj-$(CONFIG_NAND_BRCMNAND_IPROC) += iproc_nand.o
 obj-$(CONFIG_NAND_BRCMNAND) += brcmnand.o

drivers/mtd/nand/raw/brcmnand/bcm63158_nand.c

@@ -1,125 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-
-#include <asm/io.h>
-#include <memalign.h>
-#include <nand.h>
-#include <linux/bitops.h>
-#include <linux/err.h>
-#include <linux/errno.h>
-#include <linux/io.h>
-#include <linux/ioport.h>
-#include <dm.h>
-#include <linux/printk.h>
-
-#include "brcmnand.h"
-
-struct bcm63158_nand_soc {
-	struct brcmnand_soc soc;
-	void __iomem *base;
-};
-
-#define BCM63158_NAND_INT		0x00
-#define BCM63158_NAND_STATUS_SHIFT	0
-#define BCM63158_NAND_STATUS_MASK	(0xfff << BCM63158_NAND_STATUS_SHIFT)
-
-#define BCM63158_NAND_INT_EN		0x04
-#define BCM63158_NAND_ENABLE_SHIFT	0
-#define BCM63158_NAND_ENABLE_MASK	(0xffff << BCM63158_NAND_ENABLE_SHIFT)
-
-enum {
-	BCM63158_NP_READ		= BIT(0),
-	BCM63158_BLOCK_ERASE	= BIT(1),
-	BCM63158_COPY_BACK	= BIT(2),
-	BCM63158_PAGE_PGM	= BIT(3),
-	BCM63158_CTRL_READY	= BIT(4),
-	BCM63158_DEV_RBPIN	= BIT(5),
-	BCM63158_ECC_ERR_UNC	= BIT(6),
-	BCM63158_ECC_ERR_CORR	= BIT(7),
-};
-
-static bool bcm63158_nand_intc_ack(struct brcmnand_soc *soc)
-{
-	struct bcm63158_nand_soc *priv =
-			container_of(soc, struct bcm63158_nand_soc, soc);
-	void __iomem *mmio = priv->base + BCM63158_NAND_INT;
-	u32 val = brcmnand_readl(mmio);
-
-	if (val & (BCM63158_CTRL_READY << BCM63158_NAND_STATUS_SHIFT)) {
-		/* Ack interrupt */
-		val &= ~BCM63158_NAND_STATUS_MASK;
-		val |= BCM63158_CTRL_READY << BCM63158_NAND_STATUS_SHIFT;
-		brcmnand_writel(val, mmio);
-		return true;
-	}
-
-	return false;
-}
-
-static void bcm63158_nand_intc_set(struct brcmnand_soc *soc, bool en)
-{
-	struct bcm63158_nand_soc *priv =
-			container_of(soc, struct bcm63158_nand_soc, soc);
-	void __iomem *mmio = priv->base + BCM63158_NAND_INT_EN;
-	u32 val = brcmnand_readl(mmio);
-
-	/* Don't ack any interrupts */
-	val &= ~BCM63158_NAND_STATUS_MASK;
-
-	if (en)
-		val |= BCM63158_CTRL_READY << BCM63158_NAND_ENABLE_SHIFT;
-	else
-		val &= ~(BCM63158_CTRL_READY << BCM63158_NAND_ENABLE_SHIFT);
-
-	brcmnand_writel(val, mmio);
-}
-
-static int bcm63158_nand_probe(struct udevice *dev)
-{
-	struct udevice *pdev = dev;
-	struct bcm63158_nand_soc *priv = dev_get_priv(dev);
-	struct brcmnand_soc *soc;
-	struct resource res;
-
-	soc = &priv->soc;
-
-	dev_read_resource_byname(pdev, "nand-int-base", &res);
-	priv->base = devm_ioremap(dev, res.start, resource_size(&res));
-	if (IS_ERR(priv->base))
-		return PTR_ERR(priv->base);
-
-	soc->ctlrdy_ack = bcm63158_nand_intc_ack;
-	soc->ctlrdy_set_enabled = bcm63158_nand_intc_set;
-
-	/* Disable and ack all interrupts  */
-	brcmnand_writel(0, priv->base + BCM63158_NAND_INT_EN);
-	brcmnand_writel(0, priv->base + BCM63158_NAND_INT);
-
-	return brcmnand_probe(pdev, soc);
-}
-
-static const struct udevice_id bcm63158_nand_dt_ids[] = {
-	{
-		.compatible = "brcm,nand-bcm63158",
-	},
-	{ /* sentinel */ }
-};
-
-U_BOOT_DRIVER(bcm63158_nand) = {
-	.name = "bcm63158-nand",
-	.id = UCLASS_MTD,
-	.of_match = bcm63158_nand_dt_ids,
-	.probe = bcm63158_nand_probe,
-	.priv_auto	= sizeof(struct bcm63158_nand_soc),
-};
-
-void board_nand_init(void)
-{
-	struct udevice *dev;
-	int ret;
-
-	ret = uclass_get_device_by_driver(UCLASS_MTD,
-					  DM_DRIVER_GET(bcm63158_nand), &dev);
-	if (ret && ret != -ENODEV)
-		pr_err("Failed to initialize %s. (error %d)\n", dev->name,
-		       ret);
-}

drivers/mtd/nand/raw/brcmnand/bcm6753_nand.c

@@ -1,123 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-
-#include <asm/io.h>
-#include <memalign.h>
-#include <nand.h>
-#include <linux/bitops.h>
-#include <linux/errno.h>
-#include <linux/io.h>
-#include <linux/ioport.h>
-#include <dm.h>
-
-#include "brcmnand.h"
-
-struct bcm6753_nand_soc {
-	struct brcmnand_soc soc;
-	void __iomem *base;
-};
-
-#define BCM6753_NAND_INT		0x00
-#define BCM6753_NAND_STATUS_SHIFT	0
-#define BCM6753_NAND_STATUS_MASK	(0xfff << BCM6753_NAND_STATUS_SHIFT)
-
-#define BCM6753_NAND_INT_EN		0x04
-#define BCM6753_NAND_ENABLE_SHIFT	0
-#define BCM6753_NAND_ENABLE_MASK	(0xffff << BCM6753_NAND_ENABLE_SHIFT)
-
-enum {
-	BCM6753_NP_READ		= BIT(0),
-	BCM6753_BLOCK_ERASE	= BIT(1),
-	BCM6753_COPY_BACK	= BIT(2),
-	BCM6753_PAGE_PGM	= BIT(3),
-	BCM6753_CTRL_READY	= BIT(4),
-	BCM6753_DEV_RBPIN	= BIT(5),
-	BCM6753_ECC_ERR_UNC	= BIT(6),
-	BCM6753_ECC_ERR_CORR	= BIT(7),
-};
-
-static bool bcm6753_nand_intc_ack(struct brcmnand_soc *soc)
-{
-	struct bcm6753_nand_soc *priv =
-			container_of(soc, struct bcm6753_nand_soc, soc);
-	void __iomem *mmio = priv->base + BCM6753_NAND_INT;
-	u32 val = brcmnand_readl(mmio);
-
-	if (val & (BCM6753_CTRL_READY << BCM6753_NAND_STATUS_SHIFT)) {
-		/* Ack interrupt */
-		val &= ~BCM6753_NAND_STATUS_MASK;
-		val |= BCM6753_CTRL_READY << BCM6753_NAND_STATUS_SHIFT;
-		brcmnand_writel(val, mmio);
-		return true;
-	}
-
-	return false;
-}
-
-static void bcm6753_nand_intc_set(struct brcmnand_soc *soc, bool en)
-{
-	struct bcm6753_nand_soc *priv =
-			container_of(soc, struct bcm6753_nand_soc, soc);
-	void __iomem *mmio = priv->base + BCM6753_NAND_INT_EN;
-	u32 val = brcmnand_readl(mmio);
-
-	/* Don't ack any interrupts */
-	val &= ~BCM6753_NAND_STATUS_MASK;
-
-	if (en)
-		val |= BCM6753_CTRL_READY << BCM6753_NAND_ENABLE_SHIFT;
-	else
-		val &= ~(BCM6753_CTRL_READY << BCM6753_NAND_ENABLE_SHIFT);
-
-	brcmnand_writel(val, mmio);
-}
-
-static int bcm6753_nand_probe(struct udevice *dev)
-{
-	struct udevice *pdev = dev;
-	struct bcm6753_nand_soc *priv = dev_get_priv(dev);
-	struct brcmnand_soc *soc;
-	struct resource res;
-
-	soc = &priv->soc;
-
-	dev_read_resource_byname(pdev, "nand-int-base", &res);
-	priv->base = devm_ioremap(dev, res.start, resource_size(&res));
-	if (IS_ERR(priv->base))
-		return PTR_ERR(priv->base);
-
-	soc->ctlrdy_ack = bcm6753_nand_intc_ack;
-	soc->ctlrdy_set_enabled = bcm6753_nand_intc_set;
-
-	/* Disable and ack all interrupts  */
-	brcmnand_writel(0, priv->base + BCM6753_NAND_INT_EN);
-	brcmnand_writel(0, priv->base + BCM6753_NAND_INT);
-
-	return brcmnand_probe(pdev, soc);
-}
-
-static const struct udevice_id bcm6753_nand_dt_ids[] = {
-	{
-		.compatible = "brcm,nand-bcm6753",
-	},
-	{ /* sentinel */ }
-};
-
-U_BOOT_DRIVER(bcm6753_nand) = {
-	.name = "bcm6753-nand",
-	.id = UCLASS_MTD,
-	.of_match = bcm6753_nand_dt_ids,
-	.probe = bcm6753_nand_probe,
-	.priv_auto = sizeof(struct bcm6753_nand_soc),
-};
-
-void board_nand_init(void)
-{
-	struct udevice *dev;
-	int ret;
-
-	ret = uclass_get_device_by_driver(UCLASS_MTD,
-					  DM_DRIVER_GET(bcm6753_nand), &dev);
-	if (ret && ret != -ENODEV)
-		pr_err("Failed to initialize %s. (error %d)\n", dev->name,
-		       ret);
-}

drivers/mtd/nand/raw/brcmnand/bcm68360_nand.c

@@ -1,124 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-
-#include <asm/io.h>
-#include <memalign.h>
-#include <nand.h>
-#include <linux/bitops.h>
-#include <linux/errno.h>
-#include <linux/io.h>
-#include <linux/ioport.h>
-#include <dm.h>
-#include <linux/printk.h>
-
-#include "brcmnand.h"
-
-struct bcm68360_nand_soc {
-	struct brcmnand_soc soc;
-	void __iomem *base;
-};
-
-#define BCM68360_NAND_INT		0x00
-#define BCM68360_NAND_STATUS_SHIFT	0
-#define BCM68360_NAND_STATUS_MASK	(0xfff << BCM68360_NAND_STATUS_SHIFT)
-
-#define BCM68360_NAND_INT_EN		0x04
-#define BCM68360_NAND_ENABLE_SHIFT	0
-#define BCM68360_NAND_ENABLE_MASK	(0xffff << BCM68360_NAND_ENABLE_SHIFT)
-
-enum {
-	BCM68360_NP_READ		= BIT(0),
-	BCM68360_BLOCK_ERASE	= BIT(1),
-	BCM68360_COPY_BACK	= BIT(2),
-	BCM68360_PAGE_PGM	= BIT(3),
-	BCM68360_CTRL_READY	= BIT(4),
-	BCM68360_DEV_RBPIN	= BIT(5),
-	BCM68360_ECC_ERR_UNC	= BIT(6),
-	BCM68360_ECC_ERR_CORR	= BIT(7),
-};
-
-static bool bcm68360_nand_intc_ack(struct brcmnand_soc *soc)
-{
-	struct bcm68360_nand_soc *priv =
-			container_of(soc, struct bcm68360_nand_soc, soc);
-	void __iomem *mmio = priv->base + BCM68360_NAND_INT;
-	u32 val = brcmnand_readl(mmio);
-
-	if (val & (BCM68360_CTRL_READY << BCM68360_NAND_STATUS_SHIFT)) {
-		/* Ack interrupt */
-		val &= ~BCM68360_NAND_STATUS_MASK;
-		val |= BCM68360_CTRL_READY << BCM68360_NAND_STATUS_SHIFT;
-		brcmnand_writel(val, mmio);
-		return true;
-	}
-
-	return false;
-}
-
-static void bcm68360_nand_intc_set(struct brcmnand_soc *soc, bool en)
-{
-	struct bcm68360_nand_soc *priv =
-			container_of(soc, struct bcm68360_nand_soc, soc);
-	void __iomem *mmio = priv->base + BCM68360_NAND_INT_EN;
-	u32 val = brcmnand_readl(mmio);
-
-	/* Don't ack any interrupts */
-	val &= ~BCM68360_NAND_STATUS_MASK;
-
-	if (en)
-		val |= BCM68360_CTRL_READY << BCM68360_NAND_ENABLE_SHIFT;
-	else
-		val &= ~(BCM68360_CTRL_READY << BCM68360_NAND_ENABLE_SHIFT);
-
-	brcmnand_writel(val, mmio);
-}
-
-static int bcm68360_nand_probe(struct udevice *dev)
-{
-	struct udevice *pdev = dev;
-	struct bcm68360_nand_soc *priv = dev_get_priv(dev);
-	struct brcmnand_soc *soc;
-	struct resource res;
-
-	soc = &priv->soc;
-
-	dev_read_resource_byname(pdev, "nand-int-base", &res);
-	priv->base = devm_ioremap(dev, res.start, resource_size(&res));
-	if (IS_ERR(priv->base))
-		return PTR_ERR(priv->base);
-
-	soc->ctlrdy_ack = bcm68360_nand_intc_ack;
-	soc->ctlrdy_set_enabled = bcm68360_nand_intc_set;
-
-	/* Disable and ack all interrupts  */
-	brcmnand_writel(0, priv->base + BCM68360_NAND_INT_EN);
-	brcmnand_writel(0, priv->base + BCM68360_NAND_INT);
-
-	return brcmnand_probe(pdev, soc);
-}
-
-static const struct udevice_id bcm68360_nand_dt_ids[] = {
-	{
-		.compatible = "brcm,nand-bcm68360",
-	},
-	{ /* sentinel */ }
-};
-
-U_BOOT_DRIVER(bcm68360_nand) = {
-	.name = "bcm68360-nand",
-	.id = UCLASS_MTD,
-	.of_match = bcm68360_nand_dt_ids,
-	.probe = bcm68360_nand_probe,
-	.priv_auto	= sizeof(struct bcm68360_nand_soc),
-};
-
-void board_nand_init(void)
-{
-	struct udevice *dev;
-	int ret;
-
-	ret = uclass_get_device_by_driver(UCLASS_MTD,
-					  DM_DRIVER_GET(bcm68360_nand), &dev);
-	if (ret && ret != -ENODEV)
-		pr_err("Failed to initialize %s. (error %d)\n", dev->name,
-		       ret);
-}

drivers/mtd/nand/raw/brcmnand/bcm6858_nand.c

@@ -1,125 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-
-#include <asm/io.h>
-#include <memalign.h>
-#include <nand.h>
-#include <linux/bitops.h>
-#include <linux/err.h>
-#include <linux/errno.h>
-#include <linux/io.h>
-#include <linux/ioport.h>
-#include <dm.h>
-#include <linux/printk.h>
-
-#include "brcmnand.h"
-
-struct bcm6858_nand_soc {
-	struct brcmnand_soc soc;
-	void __iomem *base;
-};
-
-#define BCM6858_NAND_INT		0x00
-#define BCM6858_NAND_STATUS_SHIFT	0
-#define BCM6858_NAND_STATUS_MASK	(0xfff << BCM6858_NAND_STATUS_SHIFT)
-
-#define BCM6858_NAND_INT_EN		0x04
-#define BCM6858_NAND_ENABLE_SHIFT	0
-#define BCM6858_NAND_ENABLE_MASK	(0xffff << BCM6858_NAND_ENABLE_SHIFT)
-
-enum {
-	BCM6858_NP_READ		= BIT(0),
-	BCM6858_BLOCK_ERASE	= BIT(1),
-	BCM6858_COPY_BACK	= BIT(2),
-	BCM6858_PAGE_PGM	= BIT(3),
-	BCM6858_CTRL_READY	= BIT(4),
-	BCM6858_DEV_RBPIN	= BIT(5),
-	BCM6858_ECC_ERR_UNC	= BIT(6),
-	BCM6858_ECC_ERR_CORR	= BIT(7),
-};
-
-static bool bcm6858_nand_intc_ack(struct brcmnand_soc *soc)
-{
-	struct bcm6858_nand_soc *priv =
-			container_of(soc, struct bcm6858_nand_soc, soc);
-	void __iomem *mmio = priv->base + BCM6858_NAND_INT;
-	u32 val = brcmnand_readl(mmio);
-
-	if (val & (BCM6858_CTRL_READY << BCM6858_NAND_STATUS_SHIFT)) {
-		/* Ack interrupt */
-		val &= ~BCM6858_NAND_STATUS_MASK;
-		val |= BCM6858_CTRL_READY << BCM6858_NAND_STATUS_SHIFT;
-		brcmnand_writel(val, mmio);
-		return true;
-	}
-
-	return false;
-}
-
-static void bcm6858_nand_intc_set(struct brcmnand_soc *soc, bool en)
-{
-	struct bcm6858_nand_soc *priv =
-			container_of(soc, struct bcm6858_nand_soc, soc);
-	void __iomem *mmio = priv->base + BCM6858_NAND_INT_EN;
-	u32 val = brcmnand_readl(mmio);
-
-	/* Don't ack any interrupts */
-	val &= ~BCM6858_NAND_STATUS_MASK;
-
-	if (en)
-		val |= BCM6858_CTRL_READY << BCM6858_NAND_ENABLE_SHIFT;
-	else
-		val &= ~(BCM6858_CTRL_READY << BCM6858_NAND_ENABLE_SHIFT);
-
-	brcmnand_writel(val, mmio);
-}
-
-static int bcm6858_nand_probe(struct udevice *dev)
-{
-	struct udevice *pdev = dev;
-	struct bcm6858_nand_soc *priv = dev_get_priv(dev);
-	struct brcmnand_soc *soc;
-	struct resource res;
-
-	soc = &priv->soc;
-
-	dev_read_resource_byname(pdev, "nand-int-base", &res);
-	priv->base = devm_ioremap(dev, res.start, resource_size(&res));
-	if (IS_ERR(priv->base))
-		return PTR_ERR(priv->base);
-
-	soc->ctlrdy_ack = bcm6858_nand_intc_ack;
-	soc->ctlrdy_set_enabled = bcm6858_nand_intc_set;
-
-	/* Disable and ack all interrupts  */
-	brcmnand_writel(0, priv->base + BCM6858_NAND_INT_EN);
-	brcmnand_writel(0, priv->base + BCM6858_NAND_INT);
-
-	return brcmnand_probe(pdev, soc);
-}
-
-static const struct udevice_id bcm6858_nand_dt_ids[] = {
-	{
-		.compatible = "brcm,nand-bcm6858",
-	},
-	{ /* sentinel */ }
-};
-
-U_BOOT_DRIVER(bcm6858_nand) = {
-	.name = "bcm6858-nand",
-	.id = UCLASS_MTD,
-	.of_match = bcm6858_nand_dt_ids,
-	.probe = bcm6858_nand_probe,
-	.priv_auto	= sizeof(struct bcm6858_nand_soc),
-};
-
-void board_nand_init(void)
-{
-	struct udevice *dev;
-	int ret;
-
-	ret = uclass_get_device_by_driver(UCLASS_MTD,
-					  DM_DRIVER_GET(bcm6858_nand), &dev);
-	if (ret && ret != -ENODEV)
-		pr_err("Failed to initialize %s. (error %d)\n", dev->name,
-		       ret);
-}

drivers/mtd/nand/raw/brcmnand/brcmnand.c

@@ -1071,8 +1071,8 @@ static int bcmnand_ctrl_poll_status(struct brcmnand_controller *ctrl,
 	if ((val & mask) == expected_val)
 		return 0;
 
-	dev_warn(ctrl->dev, "timeout on status poll (expected %x got %x)\n",
-		 expected_val, val & mask);
+	dev_err(ctrl->dev, "timeout on status poll (expected %x got %x)\n",
+		expected_val, val & mask);
 
 	return -ETIMEDOUT;
 }
@@ -2032,7 +2032,7 @@ try_dmaread:
 				return err;
 		}
 
-		dev_dbg(ctrl->dev, "uncorrectable error at 0x%llx\n",
+		dev_err(ctrl->dev, "uncorrectable error at 0x%llx\n",
 			(unsigned long long)err_addr);
 		mtd->ecc_stats.failed++;
 		/* NAND layer expects zero on ECC errors */
@@ -2793,9 +2793,17 @@ int brcmnand_probe(struct udevice *dev, struct brcmnand_soc *soc)
 	nand_hw_control_init(&ctrl->controller);
 	INIT_LIST_HEAD(&ctrl->host_list);
 
+#ifdef CONFIG_NAND_BRCMNAND_BCMBCA
+	/*
+	 * BCMBCA platform does not use non-linux parameter-page-big-endian dts property,
+	 * param page data is little endian
+	 */
+	ctrl->parameter_page_big_endian = 0;
+#else
 	/* Is parameter page in big endian ? */
 	ctrl->parameter_page_big_endian =
 	    dev_read_u32_default(dev, "parameter-page-big-endian", 1);
+#endif
 
 	/* NAND register range */
 #ifndef __UBOOT__