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19 Commits

Author SHA1 Message Date
Tom Rini
7f57ad39a9 Merge tag 'u-boot-stm32-20241218' of https://source.denx.de/u-boot/custodians/u-boot-stm
CI: https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/23931

- Restore SPL boot from sdcard for STM32MP1 platforms
- Fix STACK_SIZE for STM32 MCU's board

(cherry picked from commit 69bd83568c)
2025-12-18 18:11:10 -07:00
Simon Glass
3f8d7cf3c7 Merge branch 'cherry-a8f09d62821' into 'master'
[pickman] Merge tag 'u-boot-stm32-20241218' of https://source.denx.de/u-boot/custodians/u-boot-stm

See merge request u-boot/u-boot!255
2025-12-19 01:06:34 +00:00
Tom Rini
cf2398c63a Merge tag 'u-boot-stm32-20241218' of https://source.denx.de/u-boot/custodians/u-boot-stm
CI: https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/23931

- Restore SPL boot from sdcard for STM32MP1 platforms
- Fix STACK_SIZE for STM32 MCU's board

(cherry picked from commit 69bd83568c)
2025-12-18 16:16:07 -07:00
Patrice Chotard
aa59ee4a1c configs: stm32mp1: Restore boot SPL from sdcard for Engicam i.Core STM32MP1 C.TOUCH 2.0
Restore boot SPL from sdcard for Engicam i.Core STM32MP1 C.TOUCH 2.0.

Fixes: 2a00d73d08 ("spl: mmc: Try to clean up raw-mode options")

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
(cherry picked from commit 06a8063ec9)
2025-12-18 16:15:54 -07:00
Patrice Chotard
b8fedf2a7a configs: stm32mp1: Restore boot SPL from sdcard for Engicam MicroGEA STM32MP1 MicroDev 2.0 7" OF
Restore boot SPL from sdcard for Engicam MicroGEA STM32MP1 MicroDev 2.0 7" OF

Fixes: 2a00d73d08 ("spl: mmc: Try to clean up raw-mode options")

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
(cherry picked from commit f3f14c2e3b)
2025-12-18 16:15:50 -07:00
Patrice Chotard
2fcb78c0b0 configs: stm32mp1: Restore boot SPL from sdcard for Engicam i.Core STM32MP1 EDIMM2.2
Restore boot SPL from sdcard for Engicam i.Core STM32MP1 EDIMM2.2.

Fixes: 2a00d73d08 ("spl: mmc: Try to clean up raw-mode options")

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
(cherry picked from commit fb612b4b53)
2025-12-18 16:15:44 -07:00
Patrice Chotard
c23001d2e6 configs: stm32mp1: Restore boot SPL from sdcard for Engicam i.Core STM32MP1 C.TOUCH 2.0
Restore boot SPL from sdcard for Engicam i.Core STM32MP1 C.TOUCH 2.0.

Fixes: 2a00d73d08 ("spl: mmc: Try to clean up raw-mode options")

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
(cherry picked from commit c8eacfcedc)
2025-12-18 16:15:39 -07:00
Patrice Chotard
146d6f79e8 configs: stm32mp1: Restore boot SPL from sdcard for stm32mp15
Restore boot SPL from sdcard for STM32MP1 platforms.

Fixes: 2a00d73d08 ("spl: mmc: Try to clean up raw-mode options")

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
(cherry picked from commit 7169576807)
2025-12-18 16:15:34 -07:00
Marek Vasut
230d5f597b ARM: dts: stm32: Deduplicate CONFIG_OF_SPL_REMOVE_PROPS on DH STM32MP15xx DHSOM
The content of CONFIG_OF_SPL_REMOVE_PROPS is the same in both
STM32MP15xx DHCOM and DHCOR defconfigs, deduplicate the content
into stm32mp15_dhsom.config .

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
(cherry picked from commit 5470a6a0b1)
2025-12-18 16:15:29 -07:00
Marek Vasut
795bd30801 ARM: dts: stm32: Drop access-controllers from SPL DT on DH STM32MP15xx DHSOM
The access-controllers DT property is not useful in STM32MP15xx SPL,
remove it to reduce SPL control DT size. No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
(cherry picked from commit 72c6a40fad)
2025-12-18 16:15:24 -07:00
Marek Vasut
e961327d86 ARM: dts: stm32: Reinstate SPL_SYS_MMCSD_RAW_MODE on DH STM32MP15xx DHSOM
Commit 2a00d73d08 ("spl: mmc: Try to clean up raw-mode options")
broke booting from SD card on STM32MP15xx , reinstate raw mode SD
boot configuration options and select the correct raw mode partition
for STM32MP15xx to fix SD boot on STM32MP15xx DHSOM.

Fixes: 2a00d73d08 ("spl: mmc: Try to clean up raw-mode options")
Reported-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
(cherry picked from commit dae1f13daa)
2025-12-18 16:15:16 -07:00
Marek Vasut
e66753a5d5 ARM: dts: stm32: Reinstate missing root oscillators on DH STM32MP15xx DHCOR
The root oscillators reference used to be in rcc node since
3d15245502 ("ARM: dts: stm32mp1: explicit clock reference needed by RCC clock driver")
however this is not part of upstream stm32mp151.dtsi . The
RCC driver does need this reference, reinstate it locally.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
(cherry picked from commit b651906122)
2025-12-18 16:15:11 -07:00
Marek Vasut
3f5a73a2a6 ARM: dts: stm32: Reinstate missing root oscillators on STM32MP15xx
The root oscillators reference used to be in rcc node since
3d15245502 ("ARM: dts: stm32mp1: explicit clock reference needed by RCC clock driver")
however this is not part of upstream stm32mp151.dtsi . The
RCC driver does need this reference, reinstate it globally.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
(cherry picked from commit edc425ef16)
2025-12-18 16:15:06 -07:00
Patrice Chotard
0b9953dd24 Kconfig: Set STACK_SIZE to 16KB for STM32 MCUs
Since commit 6534d26ee9 ("lmb: do away with arch_lmb_reserve()"),
STM32F746-disco hangs when loading device tree just before starting
kernel:

Retrieving file: /stm32f746-disco.dtb
Kernel image @ 0xc0008000 [ 0x000000 - 0x19ae00 ]
Flattened Device Tree blob at c0408000
   Booting using the fdt blob at 0xc0408000
Working FDT set to c0408000
   Loading Device Tree to c05f8000, end c05ff71c ...

Adjust STACK_SIZE to 16KB for STM32 MCUs (F4/F7 and H7) boards
to fix kernel boot process as some of these boards embeds a limited
amount of memory.

Fixes: 6534d26ee9 ("lmb: do away with arch_lmb_reserve()")

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
(cherry picked from commit d4ce588515)
2025-12-18 16:15:02 -07:00
Patrice Chotard
6ef642741c ARM: stm32mp: Fix dram_bank_mmu_setup() for LMB located above ram_top
Previously, all LMB marked with LMB_NOMAP (above and below ram_top)
are considered as invalid entry in TLB.

Since commit 1a48b0be93 ("lmb: prohibit allocations above ram_top
 even from same bank") all LMB located above ram_top are now marked
LMB_NOOVERWRITE and no more LMB_MAP.

This area above ram_top is reserved for OPTEE and must not be cacheable,
otherwise this leads to a Panic on some boards (Issue on STM32MP135F-DK).

Restore previous behavior by marking invalid entry all TLB above ram_top.

Fixes: 1a48b0be93 ("lmb: prohibit allocations above ram_top even from same bank")

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
cc: Sughosh Ganu <sughosh.ganu@linaro.org>
Acked-by: Sughosh Ganu <sughosh.ganu@linaro.org>
(cherry picked from commit 25fb58e88a)
2025-12-18 16:14:57 -07:00
Simon Glass
14a82d1f9e gitlab: Add an rpi to the sjg lab
I have an original rpi installed now, loaded with OS Lite (32-bit)
Add an entry for it so that it can be used for testing.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
(cherry picked from commit 1cde96bee5)
2025-12-18 16:14:51 -07:00
Simon Glass
8b35dca383 boot: Use correct PHASE_ variable for expo
This patch was written before the XPL change-over. Update the Makefile
condition to the new way.

Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: ae3b5928d6 ("x86: coreboot: Allow building an expo for...")
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
(cherry picked from commit 315fd02729)
2025-12-18 16:13:40 -07:00
Simon Glass
774976a71c test/py: Always use the current dir as the source tree
The logic in get_details() retrieves the default source directory from
the Labgrid settings. This is convenient for interactive use, since it
allows pytests to be run from any directory and still find the source
tree.

However, it is not actually correct.

Gitlab sets the current directory to the source tree and expects that to
be used. At present it is ignored. The result is that Gitlab builds
whatever happens to be in the default source directory, ignoring the
tree it is supposed to be building.

Fix this by using the directory of the source tree, always. This is
obtained by looking at the grandparent of the conftest.py file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Tom Rini <trini@konsulko.com>
Fixes: bf89a8f1fc ("test: Introduce the concept of a role")
Tested-by: Tom Rini <trini@konsulko.com>
(cherry picked from commit a8f09d6282)
2025-12-18 16:13:33 -07:00
Simon Glass
628031d445 Merge branch 'cherry-1db256a3473' into 'master'
[pickman] Merge patch series "Tegra: fix clock init"

See merge request u-boot/u-boot!254
2025-12-18 23:12:15 +00:00
13 changed files with 34 additions and 4 deletions

View File

@@ -690,6 +690,7 @@ config STACK_SIZE
hex "Define max stack size that can be used by U-Boot" hex "Define max stack size that can be used by U-Boot"
default 0x4000000 if ARCH_VERSAL_NET || ARCH_VERSAL || ARCH_ZYNQMP default 0x4000000 if ARCH_VERSAL_NET || ARCH_VERSAL || ARCH_ZYNQMP
default 0x200000 if MICROBLAZE default 0x200000 if MICROBLAZE
default 0x4000 if ARCH_STM32
default 0x1000000 default 0x1000000
help help
Define Max stack size that can be used by U-Boot. This value is used Define Max stack size that can be used by U-Boot. This value is used

View File

@@ -186,6 +186,9 @@
bootph-all; bootph-all;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clock-names = "hse", "hsi", "csi", "lse", "lsi";
clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>,
<&clk_lse>, <&clk_lsi>;
}; };
&usart1 { &usart1 {

View File

@@ -112,6 +112,10 @@
}; };
&rcc { &rcc {
clock-names = "hse", "hsi", "csi", "lse", "lsi";
clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>,
<&clk_lse>, <&clk_lsi>;
st,clksrc = < st,clksrc = <
CLK_MPU_PLL1P CLK_MPU_PLL1P
CLK_AXI_PLL2P CLK_AXI_PLL2P

View File

@@ -53,6 +53,7 @@ void dram_bank_mmu_setup(int bank)
struct bd_info *bd = gd->bd; struct bd_info *bd = gd->bd;
int i; int i;
phys_addr_t start; phys_addr_t start;
phys_addr_t addr;
phys_size_t size; phys_size_t size;
bool use_lmb = false; bool use_lmb = false;
enum dcache_option option; enum dcache_option option;
@@ -77,8 +78,12 @@ void dram_bank_mmu_setup(int bank)
for (i = start >> MMU_SECTION_SHIFT; for (i = start >> MMU_SECTION_SHIFT;
i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT); i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT);
i++) { i++) {
addr = i << MMU_SECTION_SHIFT;
option = DCACHE_DEFAULT_OPTION; option = DCACHE_DEFAULT_OPTION;
if (use_lmb && lmb_is_reserved_flags(i << MMU_SECTION_SHIFT, LMB_NOMAP)) if (use_lmb &&
(lmb_is_reserved_flags(i << MMU_SECTION_SHIFT, LMB_NOMAP) ||
addr >= gd->ram_top)
)
option = 0; /* INVALID ENTRY in TLB */ option = 0; /* INVALID ENTRY in TLB */
set_section_dcache(i, option); set_section_dcache(i, option);
} }

View File

@@ -64,7 +64,7 @@ obj-$(CONFIG_$(PHASE_)EXPO_DUMP) += expo_dump.o
obj-$(CONFIG_$(PHASE_)EXPO) += scene_menu.o scene_textline.o scene_textedit.o obj-$(CONFIG_$(PHASE_)EXPO) += scene_menu.o scene_textline.o scene_textedit.o
obj-$(CONFIG_$(PHASE_)EXPO_TEST) += expo_test.o obj-$(CONFIG_$(PHASE_)EXPO_TEST) += expo_test.o
ifdef CONFIG_COREBOOT_SYSINFO ifdef CONFIG_COREBOOT_SYSINFO
obj-$(CONFIG_$(SPL_TPL_)EXPO) += expo_build_cb.o obj-$(CONFIG_$(PHASE_)EXPO) += expo_build_cb.o
endif endif
obj-$(CONFIG_$(PHASE_)BOOTMETH_VBE) += vbe.o obj-$(CONFIG_$(PHASE_)BOOTMETH_VBE) += vbe.o

View File

@@ -28,6 +28,9 @@ CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000
CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000 CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000
CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x3
CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y CONFIG_SPL_POWER=y

View File

@@ -28,6 +28,9 @@ CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000
CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000 CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000
CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x3
CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y CONFIG_SPL_POWER=y

View File

@@ -28,6 +28,9 @@ CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000
CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000 CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000
CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x3
CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y CONFIG_SPL_POWER=y

View File

@@ -28,6 +28,9 @@ CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000
CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000 CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000
CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x3
CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y CONFIG_SPL_POWER=y

View File

@@ -39,6 +39,9 @@ CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000
CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000 CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000
CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x3
CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y CONFIG_SPL_I2C=y
CONFIG_SPL_MTD=y CONFIG_SPL_MTD=y

View File

@@ -7,5 +7,4 @@ CONFIG_SYS_MEMTEST_START=0xc0000000
CONFIG_SYS_MEMTEST_END=0xc4000000 CONFIG_SYS_MEMTEST_END=0xc4000000
CONFIG_SYS_I2C_EEPROM_BUS=3 CONFIG_SYS_I2C_EEPROM_BUS=3
CONFIG_OF_LIST="st/stm32mp157c-dhcom-pdk2 st/stm32mp153c-dhcom-drc02 st/stm32mp157c-dhcom-picoitx" CONFIG_OF_LIST="st/stm32mp157c-dhcom-pdk2 st/stm32mp153c-dhcom-drc02 st/stm32mp157c-dhcom-picoitx"
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks"
CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_SYS_I2C_EEPROM_ADDR=0x50

View File

@@ -5,7 +5,6 @@ CONFIG_ARCH_STM32MP=y
CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp157a-dhcor-avenger96" CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp157a-dhcor-avenger96"
CONFIG_SYS_I2C_EEPROM_BUS=2 CONFIG_SYS_I2C_EEPROM_BUS=2
CONFIG_OF_LIST="st/stm32mp157a-dhcor-avenger96 st/stm32mp151a-dhcor-testbench st/stm32mp153c-dhcor-drc-compact" CONFIG_OF_LIST="st/stm32mp157a-dhcor-avenger96 st/stm32mp151a-dhcor-testbench st/stm32mp153c-dhcor-drc-compact"
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks"
CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_PHY_MICREL_KSZ90X1=y

View File

@@ -22,6 +22,7 @@ CONFIG_HAS_BOARD_SIZE_LIMIT=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_HWSPINLOCK_STM32=y CONFIG_HWSPINLOCK_STM32=y
CONFIG_KS8851_MLL=y CONFIG_KS8851_MLL=y
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks access-controllers"
CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PINCTRL_STMFX=y CONFIG_PINCTRL_STMFX=y
CONFIG_REMOTEPROC_STM32_COPRO=y CONFIG_REMOTEPROC_STM32_COPRO=y
@@ -58,11 +59,14 @@ CONFIG_SPL_HAVE_INIT_STACK=y
CONFIG_SPL_STACK=0x30000000 CONFIG_SPL_STACK=0x30000000
CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000 CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000
CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SPL_TEXT_BASE=0x2FFC2500 CONFIG_SPL_TEXT_BASE=0x2FFC2500
CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_GADGET=y
CONFIG_STM32_ADC=y CONFIG_STM32_ADC=y
CONFIG_SYSRESET_SYSCON=y CONFIG_SYSRESET_SYSCON=y
CONFIG_SYS_BOOTCOUNT_ADDR=0x5C00A14C CONFIG_SYS_BOOTCOUNT_ADDR=0x5C00A14C
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x3
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MALLOC_F_LEN=0x3000 CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_PBSIZE=1050
CONFIG_PREBOOT="run dh_preboot" CONFIG_PREBOOT="run dh_preboot"