Compare commits
19 Commits
cherry-c1b
...
cherry-69e
| Author | SHA1 | Date | |
|---|---|---|---|
|
c982a158d3 | ||
|
bc29443d55 | ||
|
d550110f06 | ||
|
955abaf260 | ||
|
2c633b88c8 | ||
|
7f9fe04720 | ||
|
94040d3a94 | ||
|
47a3d716f6 | ||
|
|
0209dbd232 | ||
|
|
9586097ecb | ||
|
|
fe181b6627 | ||
|
90eeb8ab55 | ||
|
|
9a89e6a74d | ||
|
|
10a4db4696 | ||
|
c954147d94 | ||
|
|
23525e545d | ||
|
a91147f63b | ||
|
948530bdd3 | ||
|
|
de99962dc6 |
@@ -79,7 +79,7 @@ static void boot_fdt_reserve_region(u64 addr, u64 size, enum lmb_flags flags)
|
||||
debug(" reserving fdt memory region: addr=%llx size=%llx flags=%x\n",
|
||||
(unsigned long long)addr,
|
||||
(unsigned long long)size, flags);
|
||||
} else {
|
||||
} else if (ret != -EEXIST) {
|
||||
puts("ERROR: reserving fdt memory region failed ");
|
||||
printf("(addr=%llx size=%llx flags=%x)\n",
|
||||
(unsigned long long)addr,
|
||||
|
||||
@@ -183,7 +183,12 @@ static int usb_onboard_hub_bind(struct udevice *dev)
|
||||
int ret, off;
|
||||
|
||||
ret = dev_read_phandle_with_args(dev, "peer-hub", NULL, 0, 0, &phandle);
|
||||
if (ret) {
|
||||
if (ret == -ENOENT) {
|
||||
dev_dbg(dev, "peer-hub property not present\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (ret) {
|
||||
dev_err(dev, "peer-hub not specified\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
@@ -16,7 +16,6 @@ CONFIG_USB=y
|
||||
CONFIG_DM_USB_GADGET=y
|
||||
CONFIG_SPL_DM_USB_GADGET=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_SPL_USB_DWC3_GENERIC=y
|
||||
|
||||
@@ -6,6 +6,7 @@ Cool Pi GenBook is a laptop powered by RK3588, it works with a
|
||||
carrier board connect with CM5.
|
||||
|
||||
Specification:
|
||||
|
||||
* Rockchip RK3588
|
||||
* LPDDR5X 8/32 GB
|
||||
* eMMC 64 GB
|
||||
@@ -24,11 +25,11 @@ Get the TF-A and DDR init (TPL) binaries
|
||||
|
||||
.. prompt:: bash
|
||||
|
||||
> cd u-boot
|
||||
> export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.17.bin
|
||||
> export BL31=../rkbin/bin/rk35/rk3588_bl31_v1.46.elf
|
||||
> make coolpi-genbook-cm5-rk3588_defconfig
|
||||
> make CROSS_COMPILE=aarch64-linux-gnu-
|
||||
cd u-boot
|
||||
export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.17.bin
|
||||
export BL31=../rkbin/bin/rk35/rk3588_bl31_v1.46.elf
|
||||
make coolpi-genbook-cm5-rk3588_defconfig
|
||||
make CROSS_COMPILE=aarch64-linux-gnu-
|
||||
|
||||
This will build ``u-boot-rockchip.bin`` for eMMC and ``u-boot-rockchip-spi.bin`` for SPI Nor.
|
||||
|
||||
|
||||
@@ -27,6 +27,7 @@ RK3399-Q7 features:
|
||||
* Camera: 2x CSI (one on the edge connector, one on the Q7 specified CSI ZIF)
|
||||
* NOR Flash: onboard SPI NOR
|
||||
* Companion Controller: onboard additional Cortex-M0 microcontroller
|
||||
|
||||
* RTC
|
||||
* fan controller
|
||||
* CAN
|
||||
|
||||
@@ -8,6 +8,7 @@ connector) system-on-module from Theobroma Systems, featuring the
|
||||
Rockchip RK3588.
|
||||
|
||||
It provides the following feature set:
|
||||
|
||||
* up to 16GB LPDDR4x
|
||||
* on-module eMMC
|
||||
* SD card (on a baseboard) via edge connector
|
||||
@@ -18,14 +19,20 @@ It provides the following feature set:
|
||||
* HDMI input over FPC connector
|
||||
* CAN
|
||||
* USB
|
||||
|
||||
- 1x USB 3.0 dual-role (direct connection)
|
||||
- 2x USB 3.0 host + 1x USB 2.0 host
|
||||
|
||||
* PCIe
|
||||
|
||||
- 1x PCIe 2.1 Gen3, 4 lanes
|
||||
- 2xSATA / 2x PCIe 2.1 Gen1, 2 lanes
|
||||
|
||||
* on-module ATtiny816 companion controller, implementing:
|
||||
|
||||
- low-power RTC functionality (ISL1208 emulation)
|
||||
- fan controller (AMC6821 emulation)
|
||||
|
||||
* on-module Secure Element with Global Platform 2.2.1 compliant
|
||||
JavaCard environment
|
||||
|
||||
|
||||
@@ -377,7 +377,7 @@ The following are a "rule of thumb" as to how the states are used in patchwork
|
||||
today. Not all states are used by all custodians.
|
||||
|
||||
* New: Patch has been submitted to the list, and none of the maintainers has
|
||||
changed it's state since.
|
||||
changed its state since.
|
||||
|
||||
* Under Review: A custodian is reviewing the patch currently.
|
||||
|
||||
|
||||
@@ -170,7 +170,7 @@ build the tool, enable::
|
||||
|
||||
CONFIG_TOOLS_MKEFICAPSULE=y
|
||||
|
||||
Run the following commands to generate the accept/revert capsules::
|
||||
Run the following commands to generate the accept/revert capsules:
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
@@ -180,7 +180,7 @@ Run the following commands to generate the accept/revert capsules::
|
||||
<capsule_file_name>
|
||||
|
||||
Some examples of using the mkeficapsule tool for generation of the
|
||||
empty capsule would be::
|
||||
empty capsule would be:
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
|
||||
@@ -1,61 +0,0 @@
|
||||
* Rockchip RK3188/RK3066 Clock and Reset Unit
|
||||
|
||||
The RK3188/RK3066 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or
|
||||
"rockchip,rk3066a-cru"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing pll rates are not changable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
|
||||
dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
|
||||
Similar macros exist for the reset sources in these files.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "xin32k" - rtc clock - optional,
|
||||
- "xin27m" - 27mhz crystal input on rk3066 - optional,
|
||||
- "ext_hsadc" - external HSADC clock - optional,
|
||||
- "ext_cif0" - external camera clock - optional,
|
||||
- "ext_rmii" - external RMII clock - optional,
|
||||
- "ext_jtag" - externalJTAG clock - optional
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
cru: cru@20000000 {
|
||||
compatible = "rockchip,rk3188-cru";
|
||||
reg = <0x20000000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart0: serial@10124000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x10124000 0x400>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&cru SCLK_UART0>;
|
||||
};
|
||||
@@ -1,61 +0,0 @@
|
||||
* Rockchip RK3288 Clock and Reset Unit
|
||||
|
||||
The RK3288 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "rockchip,rk3288-cru"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing pll rates are not changable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "xin32k" - rtc clock - optional,
|
||||
- "ext_i2s" - external I2S clock - optional,
|
||||
- "ext_hsadc" - external HSADC clock - optional,
|
||||
- "ext_edp_24m" - external display port clock - optional,
|
||||
- "ext_vip" - external VIP clock - optional,
|
||||
- "ext_isp" - external ISP clock - optional,
|
||||
- "ext_jtag" - external JTAG clock - optional
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
cru: cru@20000000 {
|
||||
compatible = "rockchip,rk3188-cru";
|
||||
reg = <0x20000000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart0: serial@10124000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x10124000 0x400>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&cru SCLK_UART0>;
|
||||
};
|
||||
@@ -1,77 +0,0 @@
|
||||
Device Tree Clock bindings for arch-rockchip
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
== Gate clocks ==
|
||||
|
||||
These bindings are deprecated!
|
||||
Please use the soc specific CRU bindings instead.
|
||||
|
||||
The gate registers form a continuos block which makes the dt node
|
||||
structure a matter of taste, as either all gates can be put into
|
||||
one gate clock spanning all registers or they can be divided into
|
||||
the 10 individual gates containing 16 clocks each.
|
||||
The code supports both approaches.
|
||||
|
||||
Required properties:
|
||||
- compatible : "rockchip,rk2928-gate-clk"
|
||||
- reg : shall be the control register address(es) for the clock.
|
||||
- #clock-cells : from common clock binding; shall be set to 1
|
||||
- clock-output-names : the corresponding gate names that the clock controls
|
||||
- clocks : should contain the parent clock for each individual gate,
|
||||
therefore the number of clocks elements should match the number of
|
||||
clock-output-names
|
||||
|
||||
Example using multiple gate clocks:
|
||||
|
||||
clk_gates0: gate-clk@200000d0 {
|
||||
compatible = "rockchip,rk2928-gate-clk";
|
||||
reg = <0x200000d0 0x4>;
|
||||
clocks = <&dummy>, <&dummy>,
|
||||
<&dummy>, <&dummy>,
|
||||
<&dummy>, <&dummy>,
|
||||
<&dummy>, <&dummy>,
|
||||
<&dummy>, <&dummy>,
|
||||
<&dummy>, <&dummy>,
|
||||
<&dummy>, <&dummy>,
|
||||
<&dummy>, <&dummy>;
|
||||
|
||||
clock-output-names =
|
||||
"gate_core_periph", "gate_cpu_gpll",
|
||||
"gate_ddrphy", "gate_aclk_cpu",
|
||||
"gate_hclk_cpu", "gate_pclk_cpu",
|
||||
"gate_atclk_cpu", "gate_i2s0",
|
||||
"gate_i2s0_frac", "gate_i2s1",
|
||||
"gate_i2s1_frac", "gate_i2s2",
|
||||
"gate_i2s2_frac", "gate_spdif",
|
||||
"gate_spdif_frac", "gate_testclk";
|
||||
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clk_gates1: gate-clk@200000d4 {
|
||||
compatible = "rockchip,rk2928-gate-clk";
|
||||
reg = <0x200000d4 0x4>;
|
||||
clocks = <&xin24m>, <&xin24m>,
|
||||
<&xin24m>, <&dummy>,
|
||||
<&dummy>, <&xin24m>,
|
||||
<&xin24m>, <&dummy>,
|
||||
<&xin24m>, <&dummy>,
|
||||
<&xin24m>, <&dummy>,
|
||||
<&xin24m>, <&dummy>,
|
||||
<&xin24m>, <&dummy>;
|
||||
|
||||
clock-output-names =
|
||||
"gate_timer0", "gate_timer1",
|
||||
"gate_timer2", "gate_jtag",
|
||||
"gate_aclk_lcdc1_src", "gate_otgphy0",
|
||||
"gate_otgphy1", "gate_ddr_gpll",
|
||||
"gate_uart0", "gate_frac_uart0",
|
||||
"gate_uart1", "gate_frac_uart1",
|
||||
"gate_uart2", "gate_frac_uart2",
|
||||
"gate_uart3", "gate_frac_uart3";
|
||||
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@@ -1,157 +0,0 @@
|
||||
* Rockchip Pinmux Controller
|
||||
|
||||
The Rockchip Pinmux Controller, enables the IC
|
||||
to share one PAD to several functional blocks. The sharing is done by
|
||||
multiplexing the PAD input/output signals. For each PAD there are several
|
||||
muxing options with option 0 being the use as a GPIO.
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
The Rockchip pin configuration node is a node of a group of pins which can be
|
||||
used for a specific device or function. This node represents both mux and
|
||||
config of the pins in that group. The 'pins' selects the function mode(also
|
||||
named pin mode) this pin can work on and the 'config' configures various pad
|
||||
settings such as pull-up, etc.
|
||||
|
||||
The pins are grouped into up to 5 individual pin banks which need to be
|
||||
defined as gpio sub-nodes of the pinmux controller.
|
||||
|
||||
Required properties for iomux controller:
|
||||
- compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl"
|
||||
"rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl"
|
||||
"rockchip,rk3288-pinctrl"
|
||||
- rockchip,grf: phandle referencing a syscon providing the
|
||||
"general register files"
|
||||
|
||||
Optional properties for iomux controller:
|
||||
- rockchip,pmu: phandle referencing a syscon providing the pmu registers
|
||||
as some SoCs carry parts of the iomux controller registers there.
|
||||
Required for at least rk3188 and rk3288.
|
||||
|
||||
Deprecated properties for iomux controller:
|
||||
- reg: first element is the general register space of the iomux controller
|
||||
It should be large enough to contain also separate pull registers.
|
||||
second element is the separate pull register space of the rk3188.
|
||||
Use rockchip,grf and rockchip,pmu described above instead.
|
||||
|
||||
Required properties for gpio sub nodes:
|
||||
- compatible: "rockchip,gpio-bank"
|
||||
- reg: register of the gpio bank (different than the iomux registerset)
|
||||
- interrupts: base interrupt of the gpio bank in the interrupt controller
|
||||
- clocks: clock that drives this bank
|
||||
- gpio-controller: identifies the node as a gpio controller and pin bank.
|
||||
- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
|
||||
binding is used, the amount of cells must be specified as 2. See generic
|
||||
GPIO binding documentation for description of particular cells.
|
||||
- interrupt-controller: identifies the controller node as interrupt-parent.
|
||||
- #interrupt-cells: the value of this property should be 2 and the interrupt
|
||||
cells should use the standard two-cell scheme described in
|
||||
bindings/interrupt-controller/interrupts.txt
|
||||
|
||||
Deprecated properties for gpio sub nodes:
|
||||
- compatible: "rockchip,rk3188-gpio-bank0"
|
||||
- reg: second element: separate pull register for rk3188 bank0, use
|
||||
rockchip,pmu described above instead
|
||||
|
||||
Required properties for pin configuration node:
|
||||
- rockchip,pins: 3 integers array, represents a group of pins mux and config
|
||||
setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>.
|
||||
The MUX 0 means gpio and MUX 1 to N mean the specific device function.
|
||||
The phandle of a node containing the generic pinconfig options
|
||||
to use, as described in pinctrl-bindings.txt in this directory.
|
||||
|
||||
Examples:
|
||||
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
|
||||
...
|
||||
|
||||
pinctrl@20008000 {
|
||||
compatible = "rockchip,rk3066a-pinctrl";
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
gpio0: gpio0@20034000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x20034000 0x100>;
|
||||
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk_gates8 9>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
...
|
||||
|
||||
pcfg_pull_default: pcfg_pull_default {
|
||||
bias-pull-pin-default
|
||||
};
|
||||
|
||||
uart2 {
|
||||
uart2_xfer: uart2-xfer {
|
||||
rockchip,pins = <RK_GPIO1 8 1 &pcfg_pull_default>,
|
||||
<RK_GPIO1 9 1 &pcfg_pull_default>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
uart2: serial@20064000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x20064000 0x400>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&mux_uart2>;
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart2_xfer>;
|
||||
};
|
||||
|
||||
Example for rk3188:
|
||||
|
||||
pinctrl@20008000 {
|
||||
compatible = "rockchip,rk3188-pinctrl";
|
||||
rockchip,grf = <&grf>;
|
||||
rockchip,pmu = <&pmu>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
gpio0: gpio0@0x2000a000 {
|
||||
compatible = "rockchip,rk3188-gpio-bank0";
|
||||
reg = <0x2000a000 0x100>;
|
||||
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk_gates8 9>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio1: gpio1@0x2003c000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x2003c000 0x100>;
|
||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk_gates8 10>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
...
|
||||
|
||||
};
|
||||
@@ -1,68 +0,0 @@
|
||||
* Temperature Sensor ADC (TSADC) on rockchip SoCs
|
||||
|
||||
Required properties:
|
||||
- compatible : "rockchip,rk3288-tsadc"
|
||||
- reg : physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- interrupts : The interrupt number to the cpu. The interrupt specifier format
|
||||
depends on the interrupt controller.
|
||||
- clocks : Must contain an entry for each entry in clock-names.
|
||||
- clock-names : Shall be "tsadc" for the converter-clock, and "apb_pclk" for
|
||||
the peripheral clock.
|
||||
- resets : Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names : Must include the name "tsadc-apb".
|
||||
- #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description.
|
||||
- rockchip,hw-tshut-temp : The hardware-controlled shutdown temperature value.
|
||||
- rockchip,hw-tshut-mode : The hardware-controlled shutdown mode 0:CRU 1:GPIO.
|
||||
- rockchip,hw-tshut-polarity : The hardware-controlled active polarity 0:LOW
|
||||
1:HIGH.
|
||||
|
||||
Exiample:
|
||||
tsadc: tsadc@ff280000 {
|
||||
compatible = "rockchip,rk3288-tsadc";
|
||||
reg = <0xff280000 0x100>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
|
||||
clock-names = "tsadc", "apb_pclk";
|
||||
resets = <&cru SRST_TSADC>;
|
||||
reset-names = "tsadc-apb";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&otp_out>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
rockchip,hw-tshut-temp = <95000>;
|
||||
rockchip,hw-tshut-mode = <0>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
};
|
||||
|
||||
Example: referring to thermal sensors:
|
||||
thermal-zones {
|
||||
cpu_thermal: cpu_thermal {
|
||||
polling-delay-passive = <1000>; /* milliseconds */
|
||||
polling-delay = <5000>; /* milliseconds */
|
||||
|
||||
/* sensor ID */
|
||||
thermal-sensors = <&tsadc 1>;
|
||||
|
||||
trips {
|
||||
cpu_alert0: cpu_alert {
|
||||
temperature = <70000>; /* millicelsius */
|
||||
hysteresis = <2000>; /* millicelsius */
|
||||
type = "passive";
|
||||
};
|
||||
cpu_crit: cpu_crit {
|
||||
temperature = <90000>; /* millicelsius */
|
||||
hysteresis = <2000>; /* millicelsius */
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cpu_alert0>;
|
||||
cooling-device =
|
||||
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -5,10 +5,6 @@ Required properties:
|
||||
- compatible : One of:
|
||||
- brcm,bcm2835-usb: The DWC2 USB controller instance in the BCM2835 SoC.
|
||||
- hisilicon,hi6220-usb: The DWC2 USB controller instance in the hi6220 SoC.
|
||||
- rockchip,rk3066-usb: The DWC2 USB controller instance in the rk3066 Soc;
|
||||
- "rockchip,px30-usb", "rockchip,rk3066-usb", "snps,dwc2": for px30 Soc;
|
||||
- "rockchip,rk3188-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3188 Soc;
|
||||
- "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3288 Soc;
|
||||
- "lantiq,arx100-usb": The DWC2 USB controller instance in Lantiq ARX SoCs;
|
||||
- "lantiq,xrx200-usb": The DWC2 USB controller instance in Lantiq XRX SoCs;
|
||||
- "amlogic,meson8-usb": The DWC2 USB controller instance in Amlogic Meson8 SoCs;
|
||||
|
||||
@@ -1,77 +0,0 @@
|
||||
Rockchip LVDS interface
|
||||
------------------
|
||||
|
||||
Required properties:
|
||||
- compatible: "rockchip,rk3288-lvds";
|
||||
|
||||
- reg: physical base address of the controller and length
|
||||
of memory mapped region.
|
||||
- clocks: must include clock specifiers corresponding to entries in the
|
||||
clock-names property.
|
||||
- clock-names: must contain "pclk_lvds"
|
||||
|
||||
- rockchip,grf: phandle to the general register files syscon
|
||||
|
||||
- rockchip,data-mapping: should be <LVDS_FORMAT_VESA> or <LVDS_FORMAT_JEIDA>,
|
||||
This describes how the color bits are laid out in the
|
||||
serialized LVDS signal.
|
||||
- rockchip,data-width : should be <18> or <24>;
|
||||
- rockchip,output: should be <LVDS_OUTPUT_RGB>, <LVDS_OUTPUT_SINGLE> or
|
||||
<LVDS_OUTPUT_DUAL>, This describes the output face.
|
||||
|
||||
- display-timings : described by
|
||||
doc/device-tree-bindings/video/display-timing.txt.
|
||||
|
||||
Example:
|
||||
lvds: lvds@ff96c000 {
|
||||
compatible = "rockchip,rk3288-lvds";
|
||||
reg = <0xff96c000 0x4000>;
|
||||
clocks = <&cru PCLK_LVDS_PHY>;
|
||||
clock-names = "pclk_lvds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&lcdc0_ctl>;
|
||||
rockchip,grf = <&grf>;
|
||||
status = "disabled";
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
lvds_in: port@0 {
|
||||
reg = <0>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
lvds_in_vopb: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&vopb_out_lvds>;
|
||||
};
|
||||
lvds_in_vopl: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&vopl_out_lvds>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&lvds {
|
||||
rockchip,data-mapping = <LVDS_FORMAT_VESA>;
|
||||
rockchip,data-width = <24>;
|
||||
rockchip,output = <LVDS_OUTPUT_DUAL>;
|
||||
rockchip,panel = <&panel>;
|
||||
status = "okay";
|
||||
|
||||
display-timings {
|
||||
timing@0 {
|
||||
clock-frequency = <40000000>;
|
||||
hactive = <1920>;
|
||||
vactive = <1080>;
|
||||
hsync-len = <44>;
|
||||
hfront-porch = <88>;
|
||||
hback-porch = <148>;
|
||||
vfront-porch = <4>;
|
||||
vback-porch = <36>;
|
||||
vsync-len = <5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -515,12 +515,12 @@ Automatically updated variables
|
||||
-------------------------------
|
||||
|
||||
The following environment variables may be used and automatically
|
||||
updated by the network boot commands ("bootp" and "rarpboot"),
|
||||
updated by the network boot commands ("bootp", "dhcp" and "rarpboot"),
|
||||
depending the information provided by your boot server:
|
||||
|
||||
========= ===================================================
|
||||
========== ===================================================================
|
||||
Variable Notes
|
||||
========= ===================================================
|
||||
========== ===================================================================
|
||||
bootfile see above
|
||||
dnsip IP address of your Domain Name Server
|
||||
dnsip2 IP address of your secondary Domain Name Server
|
||||
@@ -530,7 +530,10 @@ ipaddr See above
|
||||
netmask Subnet Mask
|
||||
rootpath Pathname of the root filesystem on the NFS server
|
||||
serverip see above
|
||||
========= ===================================================
|
||||
ipaddrN IP address for interface N (>0) (NET_LWIP dhcp only)
|
||||
netmaskN Subnet mask for interface N (>0) (NET_LWIP dhcp only)
|
||||
gatewayipN IP address of the Gateway for interface N (>0) (NET_LWIP dhcp only)
|
||||
========== ===================================================================
|
||||
|
||||
|
||||
Special environment variables
|
||||
|
||||
@@ -321,7 +321,7 @@ static inline u32 get_pci_sync_in(immap_t *im)
|
||||
}
|
||||
|
||||
/**
|
||||
* get_csb_clk() - Read the CSB (Coheren System Bus) clock speed
|
||||
* get_csb_clk() - Read the CSB (Coherent System Bus) clock speed
|
||||
* @im: Pointer to the MPC83xx main register map in question
|
||||
*
|
||||
* Return: The CSB clock speed value as a 32-bit number.
|
||||
|
||||
@@ -11,6 +11,7 @@
|
||||
#include <dm.h>
|
||||
#include <errno.h>
|
||||
#include <generic-phy.h>
|
||||
#include <reset.h>
|
||||
#include <stdlib.h>
|
||||
#include <video.h>
|
||||
#include <wait_bit.h>
|
||||
@@ -2093,10 +2094,15 @@ static int zynqmp_dpsub_probe(struct udevice *dev)
|
||||
{
|
||||
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
|
||||
struct zynqmp_dpsub_priv *priv = dev_get_priv(dev);
|
||||
struct reset_ctl_bulk resets;
|
||||
struct clk clk;
|
||||
int ret;
|
||||
int mode = RGBA8888;
|
||||
|
||||
ret = reset_get_bulk(dev, &resets);
|
||||
if (!ret)
|
||||
reset_deassert_bulk(&resets);
|
||||
|
||||
ret = clk_get_by_name(dev, "dp_apb_clk", &clk);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to get clock\n");
|
||||
|
||||
26
lib/lmb.c
26
lib/lmb.c
@@ -182,8 +182,10 @@ static long lmb_resize_regions(struct alist *lmb_rgn_lst,
|
||||
* the function might resize an already existing region or coalesce two
|
||||
* adjacent regions.
|
||||
*
|
||||
*
|
||||
* Returns: 0 if the region addition successful, -1 on failure
|
||||
* Return:
|
||||
* * %0 - Added successfully, or it's already added (only if LMB_NONE)
|
||||
* * %-EEXIST - The region is already added, and flags != LMB_NONE
|
||||
* * %-1 - Failure
|
||||
*/
|
||||
static long lmb_add_region_flags(struct alist *lmb_rgn_lst, phys_addr_t base,
|
||||
phys_size_t size, enum lmb_flags flags)
|
||||
@@ -216,17 +218,15 @@ static long lmb_add_region_flags(struct alist *lmb_rgn_lst, phys_addr_t base,
|
||||
coalesced++;
|
||||
break;
|
||||
} else if (lmb_addrs_overlap(base, size, rgnbase, rgnsize)) {
|
||||
if (flags == LMB_NONE) {
|
||||
ret = lmb_resize_regions(lmb_rgn_lst, i, base,
|
||||
size);
|
||||
if (ret < 0)
|
||||
return -1;
|
||||
if (flags != LMB_NONE)
|
||||
return -EEXIST;
|
||||
|
||||
coalesced++;
|
||||
break;
|
||||
} else {
|
||||
ret = lmb_resize_regions(lmb_rgn_lst, i, base, size);
|
||||
if (ret < 0)
|
||||
return -1;
|
||||
}
|
||||
|
||||
coalesced++;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -664,7 +664,7 @@ long lmb_add(phys_addr_t base, phys_size_t size)
|
||||
*
|
||||
* Free up a region of memory.
|
||||
*
|
||||
* Return: 0 if successful, -1 on failure
|
||||
* Return: 0 if successful, negative error code on failure
|
||||
*/
|
||||
long lmb_free_flags(phys_addr_t base, phys_size_t size,
|
||||
uint flags)
|
||||
@@ -815,7 +815,7 @@ static phys_addr_t _lmb_alloc_addr(phys_addr_t base, phys_size_t size,
|
||||
lmb_memory[rgn].size,
|
||||
base + size - 1, 1)) {
|
||||
/* ok, reserve the memory */
|
||||
if (lmb_reserve_flags(base, size, flags) >= 0)
|
||||
if (!lmb_reserve_flags(base, size, flags))
|
||||
return base;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -754,7 +754,7 @@ static int lib_test_lmb_flags(struct unit_test_state *uts)
|
||||
|
||||
/* reserve again, same flag */
|
||||
ret = lmb_reserve_flags(0x40010000, 0x10000, LMB_NOMAP);
|
||||
ut_asserteq(ret, -1L);
|
||||
ut_asserteq(ret, -EEXIST);
|
||||
ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x10000,
|
||||
0, 0, 0, 0);
|
||||
|
||||
|
||||
Reference in New Issue
Block a user