pickman: Record cherry-pick of 13 commits from us/next

- ef9574da96 configs: Resync with savedefconfig
- 1a48b0be93 lmb: prohibit allocations above ram_top even from same bank
- 1ac2838350 rtc: CONFIGS_RTC_PL031 must depend on CONFIGS_DM_RTC
- c7401fc1d9 net: disable MBEDTLS in SPL
- 1f40dbad60 arm: qemu: fix update_info declaration
- 45f05f6812 mbedtls: remove MBEDTLS_HAVE_TIME
- 9a699a0a0d clk: rzg2l: Ignore enable for core clocks
- 2b1a5efca8 net: ravb: Simplify max-speed handling in ravb_of_to_plat
- 215663f5e4 pinctrl: rzg2l: Support 2.5V PVDD for Ethernet interfaces
- bba516a772 pinctrl: rzg2l: Support Ethernet TXC output enable
- 3a735cff5f pinctrl: rzg2l: Drop unnecessary scope
- 455e66bc59 arm64: renesas: Disable AVB1 and AVB2 on R8A779G0 V4H White Hawk board
- 497353969e Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh

.pickman-history

@@ -452,90 +452,92 @@ The branch is ready for pushing.
 
 ## 2025-12-17: us/next
 
-Branch: cherry-ccddb0abec3
+Branch: cherry-ef9574da96f
 
 Commits:
-- ccddb0abec3 power: regulator: replace some debug() by dev_dbg()
-- 74cd1af1124 power: regulator: replace dev_dbg() by dev_err() in regulator_post_bind()
-- 448add55297 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-pmic
+- ef9574da96f configs: Resync with savedefconfig
+- 1a48b0be93d lmb: prohibit allocations above ram_top even from same bank
+- 1ac28383502 rtc: CONFIGS_RTC_PL031 must depend on CONFIGS_DM_RTC
+- c7401fc1d99 net: disable MBEDTLS in SPL
+- 1f40dbad60d arm: qemu: fix update_info declaration
+- 45f05f68122 mbedtls: remove MBEDTLS_HAVE_TIME
+- 9a699a0a0d6 clk: rzg2l: Ignore enable for core clocks
+- 2b1a5efca88 net: ravb: Simplify max-speed handling in ravb_of_to_plat
+- 215663f5e47 pinctrl: rzg2l: Support 2.5V PVDD for Ethernet interfaces
+- bba516a7728 pinctrl: rzg2l: Support Ethernet TXC output enable
+- 3a735cff5f2 pinctrl: rzg2l: Drop unnecessary scope
+- 455e66bc598 arm64: renesas: Disable AVB1 and AVB2 on R8A779G0 V4H White Hawk board
+- 497353969e3 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh
 
 ### Conversation log
-The repository is clean (untracked files don't affect cherry-picking). Let me proceed with creating the new branch and cherry-picking.
+The repository is clean (only untracked files, which won't interfere). Now I'll create and checkout the new branch based on ci/master.
 
-Now let me cherry-pick the first commit:
+Now I'll cherry-pick each commit in order. Let me start with the first one:
 
-There's a conflict. Let me examine it:
+There are conflicts. Let me examine them to see if they can be auto-resolved:
 
-This is a complex conflict. The incoming commit changes the code structure and uses `dev_dbg()`, but the HEAD version has refactored the logic. Let me look at both versions more carefully:
+I can see the conflicts are related to the transition from `$(XPL_)` to `$(PHASE_)` macro naming convention in the base branch and some additional code reorganization. The incoming commit uses the older `$(XPL_)` syntax while the target branch uses `$(PHASE_)`. I need to resolve these by taking the intent of the incoming change (disabling MBEDTLS in SPL) but using the newer `$(PHASE_)` syntax.
 
-I can see the conflict clearly now. The HEAD version (ci/master) has refactored the logic to:
-- `if (regulator_name_is_unique(dev, uc_pdata->name)) return 0;`
-- Then `debug(...)` followed by `return -EINVAL;`
+Let me resolve these conflicts:
 
-The incoming commit wants to change that debug() to dev_dbg() and restructure the logic slightly.
+Good, the ci/master version already doesn't have sha256_csum_wd in sha256.c - so I should keep the HEAD version (without the incoming changes that add the function back). Let me check where sha256_csum_wd is defined in ci/master:
 
-The correct resolution should:
-1. Keep the HEAD's logic structure (use early return for unique case)
-2. But apply the change from debug() to dev_dbg() for the non-unique case
+So `sha256_csum_wd` already exists in `sha256_common.c` in ci/master. The incoming commit is trying to add it to `sha256.c` but it's already in the proper place. I should keep the HEAD version of `sha256.c` (without the function):
 
-Let me resolve this:
+Now I need to amend this commit to note the conflict resolution:
 
-First commit cherry-picked with conflict resolution. Now I need to amend the commit to note the fix-up. Let me do that:
+Now let me continue with the remaining commits:
 
-Now let's cherry-pick the second commit:
+The cherry-pick is empty - likely this change was already applied. Let me commit it empty to preserve the history:
 
-Another conflict. Let me check it:
+All 13 commits have been cherry-picked. Let me verify with git log:
 
-This is the same pattern - the second commit changes `dev_dbg()` to `dev_err()`. I need to apply this change while keeping our structure:
+All 13 commits are present. Now let me run the build verification:
 
-Now let me amend this commit to note the fix-up:
+The build succeeded with no warnings or errors. Let me provide the final status:
 
-Now let's cherry-pick the third commit (the merge commit):
+## Summary
 
-Conflict in the merge commit too. Let me examine it:
+### Cherry-pick Status: ✅ Complete
 
-The merge commit is trying to apply the same changes, but we've already applied them. Since HEAD already has `dev_err()` and the right structure, this should result in keeping our current code:
-
-The merge commit is now empty because all the changes were already applied. As instructed, we need to keep the merge commit, so I'll commit it as empty:
-
-All 3 commits cherry-picked. Now let me verify with git log:
-
-All 3 commits are present. Now let me run the build verification:
-
-The build completed successfully. Let me check for any warnings or errors:
-
-The build log is empty (no warnings or errors). The build succeeded. Let me provide a final summary:
-
-## Cherry-Pick Summary
-
-### Commits Cherry-Picked Successfully (3/3):
+All 13 commits were successfully cherry-picked from `us/next` to branch `cherry-ef9574da96f` (based on `ci/master`):
 
 | # | Hash | Subject | Status |
 |---|------|---------|--------|
-| 1 | ccddb0abec3 | power: regulator: replace some debug() by dev_dbg() | ✅ Conflict resolved |
-| 2 | 74cd1af1124 | power: regulator: replace dev_dbg() by dev_err() in regulator_post_bind() | ✅ Conflict resolved |
-| 3 | 448add55297 | Merge branch 'master' of .../u-boot-pmic | ✅ Empty (changes already applied) |
+| 1 | ef9574da96f | configs: Resync with savedefconfig | ✅ |
+| 2 | 1a48b0be93d | lmb: prohibit allocations above ram_top even from same bank | ✅ |
+| 3 | 1ac28383502 | rtc: CONFIGS_RTC_PL031 must depend on CONFIGS_DM_RTC | ✅ |
+| 4 | c7401fc1d99 | net: disable MBEDTLS in SPL | ✅ (conflict resolved) |
+| 5 | 1f40dbad60d | arm: qemu: fix update_info declaration | ✅ |
+| 6 | 45f05f68122 | mbedtls: remove MBEDTLS_HAVE_TIME | ✅ (empty - already present) |
+| 7 | 9a699a0a0d6 | clk: rzg2l: Ignore enable for core clocks | ✅ |
+| 8 | 2b1a5efca88 | net: ravb: Simplify max-speed handling in ravb_of_to_plat | ✅ |
+| 9 | 215663f5e47 | pinctrl: rzg2l: Support 2.5V PVDD for Ethernet interfaces | ✅ |
+| 10 | bba516a7728 | pinctrl: rzg2l: Support Ethernet TXC output enable | ✅ |
+| 11 | 3a735cff5f2 | pinctrl: rzg2l: Drop unnecessary scope | ✅ |
+| 12 | 455e66bc598 | arm64: renesas: Disable AVB1 and AVB2 on R8A779G0 V4H White Hawk board | ✅ |
+| 13 | 497353969e3 | Merge branch 'master' of u-boot-sh | ✅ (empty - already present) |
 
 ### Fix-ups Made:
 
-1. **Commit 1 (ccddb0abec3)**: Resolved conflict - kept ci/master's early-return logic structure (`if (regulator_name_is_unique(...)) return 0;`) while applying the `debug()` → `dev_dbg()` change.
+1. **c7401fc1d99 (net: disable MBEDTLS in SPL)**: Resolved conflicts in 5 files:
+   - `include/u-boot/sha1.h`: Kept `mbedtls_options.h` include instead of inline `MBEDTLS_ALLOW_PRIVATE_ACCESS` define
+   - `include/u-boot/sha256.h`: Kept `mbedtls_options.h` include and additional headers from HEAD
+   - `lib/Makefile`: Kept `$(PHASE_)` macro syntax instead of `$(XPL_)`
+   - `lib/lwip/Makefile`: Kept `$(PHASE_)` macro syntax instead of `$(XPL_)`
+   - `lib/sha256.c`: Kept HEAD version (sha256_csum_wd already exists in sha256_common.c)
 
-2. **Commit 2 (74cd1af1124)**: Resolved conflict - same pattern, kept ci/master's early-return logic structure while applying the `dev_dbg()` → `dev_err()` change.
+2. **45f05f68122 (mbedtls: remove MBEDTLS_HAVE_TIME)**: Empty commit - changes already present in base
 
-3. **Commit 3 (448add55297)**: Merge commit resulted in empty commit because all underlying changes were already applied in commits 1 and 2. Preserved with `--allow-empty` as instructed.
+3. **497353969e3 (Merge commit)**: Empty commit - merge changes already present in base
 
-### Build Result:
-- **Status**: ✅ OK
-- **Warnings/Errors**: None
+### Build Result: ✅ OK
+- `buildman -L --board sandbox -w -o /tmp/pickman` completed successfully with no warnings or errors
 
-### Final State:
-```
-040ca6a7c54 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-pmic
-872be1014be power: regulator: replace dev_dbg() by dev_err() in regulator_post_bind()
-505b21718ab power: regulator: replace some debug() by dev_dbg()
-```
-
-Branch `cherry-ccddb0abec3` is ready for pushing.
+### Branch Ready for Push:
+- Branch: `cherry-ef9574da96f`
+- Based on: `ci/master`
+- 13 commits ahead of `ci/master`
 
 ---
 

arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi

@@ -13,6 +13,14 @@
 	};
 };
 
+&avb1 {
+	status = "disabled";
+};
+
+&avb2 {
+	status = "disabled";
+};
+
 &rpc {
 	flash@0 {
 		spi-tx-bus-width = <1>;

board/armltd/vexpress64/Kconfig

@@ -16,8 +16,8 @@ config VEXPRESS64_BASE_MODEL
 	select VIRTIO_BLK if VIRTIO_MMIO
 	select VIRTIO_NET if VIRTIO_MMIO
 	select DM_ETH if VIRTIO_NET
+	imply DM_RTC
 	imply RTC_PL031
-	select DM_RTC if RTC_PL031
 	imply EFI_SET_TIME if DM_RTC
 	select LINUX_KERNEL_IMAGE_HEADER
 	select POSITION_INDEPENDENT

board/emulation/qemu-arm/qemu-arm.c

@@ -48,7 +48,7 @@ struct efi_fw_image fw_images[] = {
 };
 
 struct efi_capsule_update_info update_info = {
-	.num_images = ARRAY_SIZE(fw_images)
+	.num_images = ARRAY_SIZE(fw_images),
 	.images = fw_images,
 };
 

configs/bcm947622_defconfig

@@ -18,10 +18,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_OF_UPSTREAM=y
 CONFIG_OF_EMBED=y
-CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_MTD=y
 CONFIG_DM_MTD=y

configs/bcm94912_defconfig

@@ -18,10 +18,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_OF_UPSTREAM=y
 CONFIG_OF_EMBED=y
-CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_MTD=y
 CONFIG_DM_MTD=y

configs/bcm963146_defconfig

@@ -18,10 +18,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_OF_UPSTREAM=y
 CONFIG_OF_EMBED=y
-CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_MTD=y
 CONFIG_DM_MTD=y

configs/bcm963158_defconfig

@@ -18,10 +18,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_OF_UPSTREAM=y
 CONFIG_OF_EMBED=y
-CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_MTD=y
 CONFIG_DM_MTD=y

configs/bcm963178_defconfig

@@ -19,10 +19,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_OF_UPSTREAM=y
 CONFIG_OF_EMBED=y
-CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_MTD=y
 CONFIG_DM_MTD=y

configs/bcm96756_defconfig

@@ -19,10 +19,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_OF_UPSTREAM=y
 CONFIG_OF_EMBED=y
-CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_MTD=y
 CONFIG_DM_MTD=y

configs/bcm96813_defconfig

@@ -18,10 +18,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_OF_UPSTREAM=y
 CONFIG_OF_EMBED=y
-CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_MTD=y
 CONFIG_DM_MTD=y

configs/bcm96855_defconfig

@@ -19,10 +19,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_OF_UPSTREAM=y
 CONFIG_OF_EMBED=y
-CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_MTD=y
 CONFIG_DM_MTD=y

configs/bcm96856_defconfig

@@ -18,10 +18,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_OF_UPSTREAM=y
 CONFIG_OF_EMBED=y
-CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_MTD=y
 CONFIG_DM_MTD=y

configs/bcm96858_defconfig

@@ -18,10 +18,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_OF_UPSTREAM=y
 CONFIG_OF_EMBED=y
-CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_MTD=y
 CONFIG_DM_MTD=y

configs/bcm96878_defconfig

@@ -19,10 +19,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_OF_UPSTREAM=y
 CONFIG_OF_EMBED=y
-CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_MTD=y
 CONFIG_DM_MTD=y

configs/sifive_unmatched_defconfig

@@ -36,7 +36,6 @@ CONFIG_DISPLAY_BOARDINFO=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_ID_EEPROM=y
 CONFIG_PCI_INIT_R=y
-CONFIG_PCI_REGION_MULTI_ENTRY=y
 CONFIG_SPL_MAX_SIZE=0x100000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_HAVE_INIT_STACK=y
@@ -61,6 +60,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x54
 CONFIG_SPI_FLASH_ISSI=y
 CONFIG_E1000=y
 CONFIG_NVME_PCI=y
+CONFIG_PCI_REGION_MULTI_ENTRY=y
 CONFIG_PCIE_DW_SIFIVE=y
 CONFIG_SCSI=y
 CONFIG_USB=y

configs/starfive_visionfive2_defconfig

@@ -57,9 +57,6 @@ CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80000000
-CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2
 CONFIG_SPL_SYS_MALLOC_SIZE=0x400000
 CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y

drivers/clk/renesas/rzg2l-cpg.c

@@ -69,7 +69,15 @@ static int rzg2l_cpg_clk_set(struct clk *clk, bool enable)
 
 	dev_dbg(clk->dev, "%s %s clock %u\n", enable ? "enable" : "disable",
 		is_mod_clk(clk->id) ? "module" : "core", cpg_clk_id);
+
 	if (!is_mod_clk(clk->id)) {
+		/*
+		 * Non-module clocks are always on. Ignore attempts to enable
+		 * them and reject attempts to disable them.
+		 */
+		if (enable)
+			return 0;
+
 		dev_err(clk->dev, "ID %lu is not a module clock\n", clk->id);
 		return -EINVAL;
 	}

drivers/net/ravb.c

@@ -649,7 +649,6 @@ static const struct eth_ops ravb_ops = {
 int ravb_of_to_plat(struct udevice *dev)
 {
 	struct eth_pdata *pdata = dev_get_plat(dev);
-	const fdt32_t *cell;
 
 	pdata->iobase = dev_read_addr(dev);
 
@@ -657,10 +656,7 @@ int ravb_of_to_plat(struct udevice *dev)
 	if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
 		return -EINVAL;
 
-	pdata->max_speed = 1000;
-	cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
-	if (cell)
-		pdata->max_speed = fdt32_to_cpu(*cell);
+	pdata->max_speed = dev_read_u32_default(dev, "max-speed", 1000);
 
 	sprintf(bb_miiphy_buses[0].name, dev->name);
 

drivers/pinctrl/renesas/rzg2l-pfc.c

@@ -180,7 +180,7 @@ static const u32 r9a07g044_gpio_configs[] = {
 	RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS),
 	RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS),
 	RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS),
-	RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
+	RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0) | PIN_CFG_OEN),
 	RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
 	RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
 	RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
@@ -189,7 +189,7 @@ static const u32 r9a07g044_gpio_configs[] = {
 	RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
 	RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
 	RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
-	RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
+	RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1) | PIN_CFG_OEN),
 	RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
 	RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
 	RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
@@ -381,7 +381,7 @@ static int rzg2l_pinconf_set(struct udevice *dev, unsigned int pin_selector,
 	}
 
 	switch (param) {
-	case PIN_CONFIG_INPUT_ENABLE: {
+	case PIN_CONFIG_INPUT_ENABLE:
 		if (!(cfg & PIN_CFG_IEN)) {
 			dev_err(dev, "pin does not support IEN\n");
 			return -EINVAL;
@@ -391,21 +391,12 @@ static int rzg2l_pinconf_set(struct udevice *dev, unsigned int pin_selector,
 			port_offset, pin, argument);
 		rzg2l_rmw_pin_config(data, IEN(port_offset), pin, IEN_MASK, !!argument);
 		break;
-	}
 
 	case PIN_CONFIG_POWER_SOURCE: {
-		u32 pwr_reg = 0x0;
+		bool support_2500 = false;
+		u32 pwr_reg;
+		u32 value;
 
-		/* argument is in mV */
-		if (argument != 1800 && argument != 3300) {
-			dev_err(dev, "Invalid mV %u\n", argument);
-			return -EINVAL;
-		}
-
-		/*
-		 * TODO: PIN_CFG_IO_VMC_ETH0 & PIN_CFG_IO_VMC_ETH1 will be
-		 * handled when the RZ/G2L Ethernet driver is added.
-		 */
 		if (cfg & PIN_CFG_IO_VMC_SD0) {
 			dev_dbg(dev, "port off %u:%u set SD_CH 0 PVDD=%u\n",
 				port_offset, pin, argument);
@@ -418,13 +409,68 @@ static int rzg2l_pinconf_set(struct udevice *dev, unsigned int pin_selector,
 			dev_dbg(dev, "port off %u:%u set QSPI PVDD=%u\n",
 				port_offset, pin, argument);
 			pwr_reg = QSPI;
+		} else if (cfg & PIN_CFG_IO_VMC_ETH0) {
+			dev_dbg(dev, "port off %u:%u set ETH0 PVDD=%u\n",
+				port_offset, pin, argument);
+			pwr_reg = ETH_POC(0);
+			support_2500 = true;
+		} else if (cfg & PIN_CFG_IO_VMC_ETH1) {
+			dev_dbg(dev, "port off %u:%u set ETH1 PVDD=%u\n",
+				port_offset, pin, argument);
+			pwr_reg = ETH_POC(1);
+			support_2500 = true;
 		} else {
-			dev_dbg(dev, "pin power source is not selectable\n");
+			dev_dbg(dev, "port off %u:%u PVDD is not selectable\n",
+				port_offset, pin);
 			return -EINVAL;
 		}
 
-		writel((argument == 1800) ? PVDD_1800 : PVDD_3300,
-		       data->base + pwr_reg);
+		/* argument is in mV */
+		switch (argument) {
+		case 1800:
+			value = PVDD_1800;
+			break;
+		case 3300:
+			value = PVDD_3300;
+			break;
+		case 2500:
+			if (support_2500) {
+				value = PVDD_2500;
+				break;
+			}
+			fallthrough;
+		default:
+			dev_err(dev, "Invalid mV %u\n", argument);
+			return -EINVAL;
+		}
+
+		writel(value, data->base + pwr_reg);
+		break;
+	}
+
+	case PIN_CONFIG_OUTPUT_ENABLE: {
+		u8 ch;
+
+		if (!(cfg & PIN_CFG_OEN)) {
+			dev_err(dev, "pin does not support OEN\n");
+			return -EINVAL;
+		}
+
+		/*
+		 * We can determine which Ethernet interface we're dealing with from
+		 * the caps.
+		 */
+		if (cfg & PIN_CFG_IO_VMC_ETH0)
+			ch = 0;
+		else /* PIN_CFG_IO_VMC_ETH1 */
+			ch = 1;
+
+		dev_dbg(dev, "set ETH%u TXC OEN=%u\n", ch, argument);
+		if (argument)
+			clrbits_8(data->base + ETH_MODE, BIT(ch));
+		else
+			setbits_8(data->base + ETH_MODE, BIT(ch));
+
 		break;
 	}
 
@@ -521,6 +567,7 @@ static int rzg2l_get_pin_muxing(struct udevice *dev, unsigned int selector,
 
 static const struct pinconf_param rzg2l_pinconf_params[] = {
 	{ "input-enable",	PIN_CONFIG_INPUT_ENABLE,	1 },
+	{ "output-enable",	PIN_CONFIG_OUTPUT_ENABLE,	1 },
 	{ "power-source",	PIN_CONFIG_POWER_SOURCE,	3300 /* mV */ },
 };
 

drivers/rtc/Kconfig

@@ -203,6 +203,7 @@ config RTC_RX8025
 
 config RTC_PL031
 	bool "Enable ARM AMBA PL031 RTC driver"
+	depends on DM_RTC
 	help
 	  The ARM PrimeCell Real Time Clock (PL031) is an optional SoC
 	  peripheral based on the Advanced Microcontroller Bus Architecture

include/renesas/rzg2l-pfc.h

@@ -22,6 +22,7 @@
 #define PIN_CFG_FILONOFF		BIT(10)
 #define PIN_CFG_FILNUM			BIT(11)
 #define PIN_CFG_FILCLKSEL		BIT(12)
+#define PIN_CFG_OEN			BIT(13)
 
 #define RZG2L_MPXED_PIN_FUNCS		(PIN_CFG_IOLH_A | \
 					 PIN_CFG_SR | \
@@ -77,9 +78,12 @@
 #define IEN(n)			(0x1800 + (n) * 8)
 #define PWPR			0x3014
 #define SD_CH(n)		(0x3000 + (n) * 4)
+#define ETH_POC(ch)		(0x300c + (ch) * 4)
 #define QSPI			0x3008
+#define ETH_MODE		0x3018
 
 #define PVDD_1800		1	/* I/O domain voltage <= 1.8V */
+#define PVDD_2500		2	/* I/O domain voltage 2.5V */
 #define PVDD_3300		0	/* I/O domain voltage >= 3.3V */
 
 #define PWPR_B0WI		BIT(7)	/* Bit Write Disable */

include/u-boot/md5.h

@@ -6,7 +6,9 @@
 #ifndef _MD5_H
 #define _MD5_H
 
-#if defined(CONFIG_MBEDTLS_LIB_CRYPTO)
+#include <linux/kconfig.h>
+
+#if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO)
 #include <mbedtls/md5.h>
 #endif
 #include "compiler.h"
@@ -14,7 +16,7 @@
 #define MD5_SUM_LEN	16
 #define MD5_DEF_CHUNK_SZ 0x10000
 
-#if defined(CONFIG_MBEDTLS_LIB_CRYPTO)
+#if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO)
 typedef mbedtls_md5_context MD5Context;
 #else
 typedef struct MD5Context {

include/u-boot/sha512.h

@@ -1,9 +1,10 @@
 #ifndef _SHA512_H
 #define _SHA512_H
 
+#include <linux/kconfig.h>
 #include <linux/types.h>
 
-#if defined(CONFIG_MBEDTLS_LIB_CRYPTO)
+#if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO)
 #include <mbedtls/sha512.h>
 #endif
 
@@ -16,7 +17,7 @@
 #define CHUNKSZ_SHA384	(16 * 1024)
 #define CHUNKSZ_SHA512	(16 * 1024)
 
-#if defined(CONFIG_MBEDTLS_LIB_CRYPTO)
+#if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO)
 typedef mbedtls_sha512_context sha384_context;
 typedef mbedtls_sha512_context sha512_context;
 #else

lib/lmb.c

@@ -603,6 +603,7 @@ static __maybe_unused void lmb_reserve_common_spl(void)
 void lmb_add_memory(void)
 {
 	int i;
+	phys_addr_t bank_end;
 	phys_size_t size;
 	u64 ram_top = gd->ram_top;
 	struct bd_info *bd = gd->bd;
@@ -616,6 +617,8 @@ void lmb_add_memory(void)
 
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 		size = bd->bi_dram[i].size;
+		bank_end = bd->bi_dram[i].start + size;
+
 		if (size) {
 			lmb_add(bd->bi_dram[i].start, size);
 
@@ -627,6 +630,9 @@ void lmb_add_memory(void)
 			if (bd->bi_dram[i].start >= ram_top)
 				lmb_reserve_flags(bd->bi_dram[i].start, size,
 						  LMB_NOOVERWRITE);
+			else if (bank_end > ram_top)
+				lmb_reserve_flags(ram_top, bank_end - ram_top,
+						  LMB_NOOVERWRITE);
 		}
 	}
 }

lib/lwip/u-boot/lwipopts.h

@@ -5,6 +5,8 @@
 #ifndef LWIP_UBOOT_LWIPOPTS_H
 #define LWIP_UBOOT_LWIPOPTS_H
 
+#include <linux/kconfig.h>
+
 #if defined(CONFIG_LWIP_DEBUG)
 #define LWIP_DEBUG 1
 #define LWIP_DBG_MIN_LEVEL              LWIP_DBG_LEVEL_ALL
@@ -154,7 +156,7 @@
 #define MEMP_MEM_INIT			1
 #define MEM_LIBC_MALLOC			1
 
-#if defined(CONFIG_MBEDTLS_LIB_TLS)
+#if CONFIG_IS_ENABLED(MBEDTLS_LIB_TLS)
 #define LWIP_ALTCP                      1
 #define LWIP_ALTCP_TLS                  1
 #define LWIP_ALTCP_TLS_MBEDTLS          1

lib/md5.c

@@ -272,14 +272,16 @@ md5_wd(const unsigned char *input, unsigned int len, unsigned char output[16],
 	unsigned int chunk_sz)
 {
 	MD5Context context;
-#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+#if !defined(USE_HOSTCC) && \
+    (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG))
 	const unsigned char *end, *curr;
 	int chunk;
 #endif
 
 	MD5Init(&context);
 
-#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+#if !defined(USE_HOSTCC) && \
+    (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG))
 	curr = input;
 	end = input + len;
 	while (curr < end) {

lib/sha512.c

@@ -288,7 +288,8 @@ void sha384_csum_wd(const unsigned char *input, unsigned int ilen,
 		unsigned char *output, unsigned int chunk_sz)
 {
 	sha512_context ctx;
-#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+#if !defined(USE_HOSTCC) && \
+    (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG))
 	const unsigned char *end;
 	unsigned char *curr;
 	int chunk;
@@ -296,7 +297,8 @@ void sha384_csum_wd(const unsigned char *input, unsigned int ilen,
 
 	sha384_starts(&ctx);
 
-#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+#if !defined(USE_HOSTCC) && \
+    (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG))
 	curr = (unsigned char *)input;
 	end = input + ilen;
 	while (curr < end) {
@@ -351,7 +353,8 @@ void sha512_csum_wd(const unsigned char *input, unsigned int ilen,
 		unsigned char *output, unsigned int chunk_sz)
 {
 	sha512_context ctx;
-#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+#if !defined(USE_HOSTCC) && \
+    (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG))
 	const unsigned char *end;
 	unsigned char *curr;
 	int chunk;
@@ -359,7 +362,8 @@ void sha512_csum_wd(const unsigned char *input, unsigned int ilen,
 
 	sha512_starts(&ctx);
 
-#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+#if !defined(USE_HOSTCC) && \
+    (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG))
 	curr = (unsigned char *)input;
 	end = input + ilen;
 	while (curr < end) {