bloblist: Allow using a different bloblist address

Where the bloblist is located in internal memory and TF-A's BL31 blob
removes access to this memory, the best option seems to be to relocate
the bloblist just before running TF-A.

We can do the relocation in board-specific code, but need an option to
pick up the correct address within U-Boot proper.

Series-changes: 2
- Move the actual relocation code to a previous board-specific patch

Series-to: u-boot
Series-links: 442878
Series-version: 2
Cover-letter:
VBE serial part H: Implement VBE on Rockchip RK3399
This series completes the work to enable VBE on a suitable board. Most
of it is rockchip-specific patches to support the VPL phase, i.e. the
one which decides which boot patch to take (A, B or recovery).

A good chunk of this series is adding an image for VBE, by creating a
new Binman image. Future work in Binman may make this more automated /
easier, but for now it is written out in full. The work is undertaken
piecemeal so it is easier to review the steps.

VBE allows similar boards to share firmware images, with perhaps just
TPL (around 75K) being different for each board. Using a common image
for VPL, SPL and U-Boot saves a lot of space in the image and makes
builds easier. Of course, each board still needs a separate devicetree.

Here is the layout of the image:

Name                          Image-pos  Size      Entry-type          Offset    Uncomp-size
----------------------------------------------------------------------------------------------
image                                 0   1b960cf  section                    0
  alternates-fdt                   8000     31000  alternates-fdt          8000
    mkimage                        8000     31000  mkimage                    0
      u-boot-tpl                   8048     12a11  u-boot-tpl                48
  vpl                            208000     16200  fit                   208000
    image-vpl                    209400      a5a3  section                 1400
      section                    209400      a5a3  section                    0
        u-boot-vpl-nodtb                    10348  u-boot-vpl-nodtb           0
        u-boot-vpl-bss-pad                     20  u-boot-vpl-bss-pad     10348
    @fdt-SEQ                          0         0  section                    0
  vbe-a                          800000    39b200  section               800000
    spl-a                        800000    100000  fit                        0
      spl                        801400     10c97  section                 1400
        section                  801400     10c97  section                    0
          u-boot-spl-nodtb                  1a908  u-boot-spl-nodtb           0
          u-boot-spl-bss-pad                  1b0  u-boot-spl-bss-pad     1a908
      @fdt-SEQ                        0         0  section                    0
    u-boot-a                     900000    29b200  fit                   100000
      spl                        902400     10c97  section                 2400
        section                  902400     10c97  section                    0
          u-boot-spl-nodtb                  1a908  u-boot-spl-nodtb           0
          u-boot-spl-bss-pad                  1b0  u-boot-spl-bss-pad     1a908
      u-boot                     913200     e4250  section                13200
        u-boot-nodtb             913200     e4250  u-boot-nodtb               0
      @atf-SEQ                        0         0  section                    0
        atf-bl31                      0         0  atf-bl31                   0
      @tee-SEQ                        0         0  section                    0
        tee-os                        0         0  tee-os                     0
      @fdt-SEQ                        0         0  section                    0
  vbe-b                         1000000    39b200  section              1000000
    spl-b                       1000000    100000  fit                        0
      spl                       1001400     10c97  section                 1400
        section                 1001400     10c97  section                    0
          u-boot-spl-nodtb                  1a908  u-boot-spl-nodtb           0
          u-boot-spl-bss-pad                  1b0  u-boot-spl-bss-pad     1a908
      @fdt-SEQ                        0         0  section                    0
    u-boot-b                    1100000    29b200  fit                   100000
      spl                       1102400     10c97  section                 2400
        section                 1102400     10c97  section                    0
          u-boot-spl-nodtb                  1a908  u-boot-spl-nodtb           0
          u-boot-spl-bss-pad                  1b0  u-boot-spl-bss-pad     1a908
      u-boot                    1113200     e4250  section                13200
        u-boot-nodtb            1113200     e4250  u-boot-nodtb               0
      @atf-SEQ                        0         0  section                    0
        atf-bl31                      0         0  atf-bl31                   0
      @tee-SEQ                        0         0  section                    0
        tee-os                        0         0  tee-os                     0
      @fdt-SEQ                        0         0  section                    0
  vbe-recovery                  1800000    39b200  section              1800000
    spl-recovery                1800000    100000  fit                        0
      spl                       1801400     10c97  section                 1400
        section                 1801400     10c97  section                    0
          u-boot-spl-nodtb                  1a908  u-boot-spl-nodtb           0
          u-boot-spl-bss-pad                  1b0  u-boot-spl-bss-pad     1a908
      @fdt-SEQ                        0         0  section                    0
    u-boot-recovery             1900000    29b200  fit                   100000
      spl                       1902400     10c97  section                 2400
        section                 1902400     10c97  section                    0
          u-boot-spl-nodtb                  1a908  u-boot-spl-nodtb           0
          u-boot-spl-bss-pad                  1b0  u-boot-spl-bss-pad     1a908
      u-boot                    1913200     e4250  section                13200
        u-boot-nodtb            1913200     e4250  u-boot-nodtb               0
      @atf-SEQ                        0         0  section                    0
        atf-bl31                      0         0  atf-bl31                   0
      @tee-SEQ                        0         0  section                    0
        tee-os                        0         0  tee-os                     0
      @fdt-SEQ                        0         0  section                    0
  fdtmap                        1b9b200      2ecf  fdtmap               1b9b200

Unfortunately I got a bit lost trying to figure out the bloblist code,
despite my being the original author. So for now I have included a
revert of a recent patch, so that the logic can be simplified and more
in keeping with the original intent. We may in fact need a symbol which
specifically says which phase creates the bloblist, but I'm not
completely sure of what the reverted patch was trying to achieve.

This is (mostly) the final VBE series, but there are a few loose ends to
tidy up:

- cache is disabled in SPL, which slows the boot a little
- pinctrl init needs to be tidied up to avoid warnings
- bloblist logic as above
- bloblist-relocation is partly in board-specific code, partly generic

Other things may become apparently after more usage / testing.
END
Signed-off-by: Simon Glass <sjg@chromium.org>

.gitlab-ci.yml

@@ -745,3 +745,9 @@ zybo:
   variables:
     ROLE: zybo
   <<: *lab_dfn
+
+# Firefly-RK3399 board running the rk3399-generic build
+vbe:
+  variables:
+    ROLE: vbe
+  <<: *lab_dfn

arch/arm/cpu/armv7/lowlevel_init.S

@@ -26,8 +26,8 @@ WEAK(lowlevel_init)
 	/*
 	 * Setup a temporary stack. Global data is not available yet.
 	 */
-#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK)
-	ldr	sp, =CONFIG_SPL_STACK
+#if CONFIG_IS_ENABLED(HAVE_INIT_STACK)
+	ldr	sp, =CONFIG_VAL(STACK)
 #else
 	ldr	sp, =SYS_INIT_SP_ADDR
 #endif

arch/arm/cpu/armv7/start.S

@@ -279,8 +279,8 @@ ENTRY(cpu_init_cp15)
 	orr	r2, r4, r2		@ r2 has combined CPU variant + revision
 
 /* Early stack for ERRATA that needs into call C code */
-#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK)
-	ldr	r0, =(CONFIG_SPL_STACK)
+#if CONFIG_IS_ENABLED(HAVE_INIT_STACK)
+	ldr	r0, =CONFIG_VAL(STACK)
 #else
 	ldr	r0, =(SYS_INIT_SP_ADDR)
 #endif

arch/arm/dts/rk3399-u-boot.dtsi

@@ -71,7 +71,12 @@
 	       0x0 0xffa88800 0x0 0x1800
 	       0x0 0xffa8a000 0x0 0x2000
 	       0x0 0xffa8c000 0x0 0x1000>;
-	bootph-all;
+#ifdef CONFIG_VPL
+		bootph-pre-ram;
+		bootph-some-ram;
+#else
+		bootph-all;
+#endif
 	status = "okay";
 };
 
@@ -118,6 +123,10 @@
 };
 
 &sdmmc {
+#ifdef CONFIG_VPL
+	bootph-pre-sram;
+	bootph-verify;
+#endif
 	bootph-pre-ram;
 	bootph-some-ram;
 

arch/arm/dts/rockchip-u-boot.dtsi

@@ -5,6 +5,24 @@
 
 #include <config.h>
 
+#ifdef CONFIG_ARM64
+#define ARCH	"arm64"
+#else
+#define ARCH	"arm"
+#endif
+
+#if defined(CONFIG_SPL_GZIP)
+#define COMP	"gzip"
+#elif defined(CONFIG_SPL_LZMA)
+#define COMP	"lzma"
+#else
+#define COMP	"none"
+#endif
+
+#if defined(CONFIG_SPL_FIT) && (defined(CONFIG_ARM64) || defined(CONFIG_SPL_OPTEE_IMAGE))
+#define HAS_FIT
+#endif
+
 / {
 	binman: binman {
 		multiple-images;
@@ -13,10 +31,179 @@
 
 #ifdef CONFIG_SPL
 &binman {
+#ifdef HAS_FIT
+	common_part: template-1 {
+		type = "fit";
+#ifdef CONFIG_ARM64
+		description = "FIT image for U-Boot with bl31 (TF-A)";
+#else
+		description = "FIT image with OP-TEE";
+#endif
+		#address-cells = <1>;
+		fit,fdt-list = "of-list";
+		fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+		fit,align = <512>;
+		images {
+			u-boot {
+				description = "U-Boot";
+				type = "standalone";
+				os = "u-boot";
+				arch = ARCH;
+				compression = COMP;
+				load = <CONFIG_TEXT_BASE>;
+				entry = <CONFIG_TEXT_BASE>;
+				phase = "u-boot";
+				u-boot-nodtb {
+					compress = COMP;
+				};
+#ifdef CONFIG_SPL_FIT_SIGNATURE
+				hash {
+					algo = "sha256";
+				};
+#endif
+			};
+
+#ifdef CONFIG_ARM64
+			@atf-SEQ {
+				fit,operation = "split-elf";
+				description = "ARM Trusted Firmware";
+				type = "firmware";
+				arch = ARCH;
+				os = "arm-trusted-firmware";
+				compression = "none";
+				phase = "u-boot";
+				fit,load;
+				fit,entry;
+				fit,data;
+
+				atf-bl31 {
+				};
+#ifdef CONFIG_SPL_FIT_SIGNATURE
+				hash {
+					algo = "sha256";
+				};
+#endif
+			};
+			@tee-SEQ {
+				fit,operation = "split-elf";
+				description = "TEE";
+				type = "tee";
+				arch = ARCH;
+				os = "tee";
+				compression = "none";
+				phase = "u-boot";
+				fit,load;
+				fit,entry;
+				fit,data;
+
+				tee-os {
+					optional;
+				};
+#ifdef CONFIG_SPL_FIT_SIGNATURE
+				hash {
+					algo = "sha256";
+				};
+#endif
+			};
+#else /* !CONFIG_ARM64 */
+			op-tee {
+				description = "OP-TEE";
+				type = "tee";
+				arch = ARCH;
+				os = "tee";
+				compression = "none";
+				load = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
+				entry = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
+				phase = "u-boot";
+
+				tee-os {
+				};
+#ifdef CONFIG_SPL_FIT_SIGNATURE
+				hash {
+					algo = "sha256";
+				};
+#endif
+			};
+#endif /* CONFIG_ARM64 */
+
+			@fdt-SEQ {
+				description = "fdt-NAME";
+				compression = "none";
+				type = "flat_dt";
+#ifdef CONFIG_SPL_FIT_SIGNATURE
+				hash {
+					algo = "sha256";
+				};
+#endif
+			};
+		};
+
+		configurations {
+			default = "@config-DEFAULT-SEQ";
+			@config-SEQ {
+				description = "NAME.dtb";
+				fdt = "fdt-SEQ";
+#ifdef CONFIG_ARM64
+				fit,firmware = "atf-1", "u-boot";
+#else
+				fit,firmware = "op-tee", "u-boot";
+#endif
+				fit,loadables;
+				fit,compatible;
+			};
+		};
+	};
+
+	spl_template: template-2 {
+		type = "fit";
+		description = "FIT image for U-Boot SPL";
+		#address-cells = <1>;
+		fit,fdt-list = "of-list";
+		fit,align = <512>;
+		fit,external-offset = <0>;
+		images {
+			spl {
+				description = "U-Boot SPL";
+				type = "firmware";
+				os = "u-boot";
+				arch = ARCH;
+				compression = "lz4";
+				load = <CONFIG_SPL_TEXT_BASE>;
+				entry = <CONFIG_SPL_TEXT_BASE>;
+				section {
+					compress = "lz4";
+					u-boot-spl-nodtb {
+					};
+					u-boot-spl-bss-pad {
+					};
+				};
+			};
+			@fdt-SEQ {
+				description = "fdt-NAME";
+				compression = "none";
+				type = "flat_dt";
+				fit,fdt-phase = "spl";
+			};
+		};
+		configurations {
+			default = "@config-DEFAULT-SEQ";
+			@config-SEQ {
+				description = "NAME.dtb";
+				fdt = "fdt-SEQ";
+				fit,firmware = "spl";
+				fit,loadables;
+				fit,compatible;
+			};
+		};
+	};
+#endif /* HAS_FIT */
+
 	simple-bin {
 		filename = "u-boot-rockchip.bin";
 		pad-byte = <0xff>;
+		skip-at-start = <0x8000>;
 
+#ifndef CONFIG_VPL
 		mkimage {
 			filename = "idbloader.img";
 			args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
@@ -33,143 +220,19 @@
 			};
 		};
 
-#if defined(CONFIG_SPL_FIT) && (defined(CONFIG_ARM64) || defined(CONFIG_SPL_OPTEE_IMAGE))
-		fit: fit {
-#ifdef CONFIG_ARM64
-			description = "FIT image for U-Boot with bl31 (TF-A)";
-#else
-			description = "FIT image with OP-TEE";
-#endif
-			#address-cells = <1>;
-			fit,fdt-list = "of-list";
-			filename = "u-boot.itb";
-			fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
-			fit,align = <512>;
+#ifdef HAS_FIT
+		fit {
 			offset = <CONFIG_SPL_PAD_TO>;
-			images {
-				u-boot {
-					description = "U-Boot";
-					type = "standalone";
-					os = "U-Boot";
-#ifdef CONFIG_ARM64
-					arch = "arm64";
-#else
-					arch = "arm";
-#endif
-#if defined(CONFIG_SPL_GZIP)
-					compression = "gzip";
-#elif defined(CONFIG_SPL_LZMA)
-					compression = "lzma";
-#else
-					compression = "none";
-#endif
-					load = <CONFIG_TEXT_BASE>;
-					entry = <CONFIG_TEXT_BASE>;
-					u-boot-nodtb {
-#if defined(CONFIG_SPL_GZIP)
-					compress = "gzip";
-#elif defined(CONFIG_SPL_LZMA)
-					compress = "lzma";
-#endif
-					};
-#ifdef CONFIG_SPL_FIT_SIGNATURE
-					hash {
-						algo = "sha256";
-					};
-#endif
-				};
-
-#ifdef CONFIG_ARM64
-				@atf-SEQ {
-					fit,operation = "split-elf";
-					description = "ARM Trusted Firmware";
-					type = "firmware";
-					arch = "arm64";
-					os = "arm-trusted-firmware";
-					compression = "none";
-					fit,load;
-					fit,entry;
-					fit,data;
-
-					atf-bl31 {
-					};
-#ifdef CONFIG_SPL_FIT_SIGNATURE
-					hash {
-						algo = "sha256";
-					};
-#endif
-				};
-				@tee-SEQ {
-					fit,operation = "split-elf";
-					description = "TEE";
-					type = "tee";
-					arch = "arm64";
-					os = "tee";
-					compression = "none";
-					fit,load;
-					fit,entry;
-					fit,data;
-
-					tee-os {
-						optional;
-					};
-#ifdef CONFIG_SPL_FIT_SIGNATURE
-					hash {
-						algo = "sha256";
-					};
-#endif
-				};
-#else
-				op-tee {
-					description = "OP-TEE";
-					type = "tee";
-					arch = "arm";
-					os = "tee";
-					compression = "none";
-					load = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
-					entry = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
-
-					tee-os {
-					};
-#ifdef CONFIG_SPL_FIT_SIGNATURE
-					hash {
-						algo = "sha256";
-					};
-#endif
-				};
-#endif
-
-				@fdt-SEQ {
-					description = "fdt-NAME";
-					compression = "none";
-					type = "flat_dt";
-#ifdef CONFIG_SPL_FIT_SIGNATURE
-					hash {
-						algo = "sha256";
-					};
-#endif
-				};
-			};
-
-			configurations {
-				default = "@config-DEFAULT-SEQ";
-				@config-SEQ {
-					description = "NAME.dtb";
-					fdt = "fdt-SEQ";
-#ifdef CONFIG_ARM64
-					fit,firmware = "atf-1", "u-boot";
-#else
-					fit,firmware = "op-tee", "u-boot";
-#endif
-					fit,loadables;
-				};
-			};
+			insert-template = <&common_part>;
 		};
 #else
 		u-boot-img {
 			offset = <CONFIG_SPL_PAD_TO>;
 		};
-#endif
+#endif /* HAS_FIT */
+#endif /* VPL */
+		fdtmap {
+		};
 	};
 
 #ifdef CONFIG_ROCKCHIP_SPI_IMAGE
@@ -195,15 +258,20 @@
 
 #if defined(CONFIG_ARM64) || defined(CONFIG_SPL_OPTEE_IMAGE)
 		fit {
-			type = "blob";
-			filename = "u-boot.itb";
+			insert-template = <&common_part>;
 #else
 		u-boot-img {
 #endif
 			/* Sync with u-boot,spl-payload-offset if present */
 			offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;
 		};
+		fdtmap {
+		};
 	};
 #endif /* CONFIG_ROCKCHIP_SPI_IMAGE */
 };
 #endif /* CONFIG_SPL */
+
+#ifdef CONFIG_VPL
+#include "rockchip-vpl-u-boot.dtsi"
+#endif

arch/arm/dts/rockchip-vpl-u-boot.dtsi

@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+/ {
+	bootstd {
+		bootph-verify;
+		compatible = "u-boot,boot-std";
+
+		/*
+		 * This is used for the VBE OS-request tests. A FAT filesystem
+		 * created in a partition with the VBE information appearing
+		 * before the partition starts.
+		 *
+		 * Offsets are aligned to the media block-size, typically 0x200
+		 */
+		firmware0 {
+			bootph-verify;
+			compatible = "fwupd,vbe-abrec";
+			storage = "mmc0";
+			area-start = <CONFIG_SPL_PAD_TO>;
+			area-size = <0x800000>;
+			state-offset = <(CONFIG_SPL_PAD_TO - 0x400)>;
+			state-size = <0x40>;
+			version-offset = <(CONFIG_SPL_PAD_TO - 0x200)>;
+			version-size = <0x100>;
+		};
+	};
+};
+
+&binman {
+	template-1 {
+		images {
+			spl {
+				description = "U-Boot SPL";
+				type = "firmware";
+				os = "u-boot";
+				arch = ARCH;
+				compression = "lz4";
+				load = <CONFIG_SPL_TEXT_BASE>;
+				entry = <CONFIG_SPL_TEXT_BASE>;
+				phase = "spl";
+				section {
+					compress = "lz4";
+					u-boot-spl-nodtb {
+					};
+					u-boot-spl-bss-pad {
+					};
+				};
+			};
+		};
+		configurations {
+			@config-SEQ {
+				fit,firmware = "atf-1", "u-boot", "spl";
+			};
+		};
+	};
+
+	simple-bin {
+		alternates-fdt {
+			fdt-list-dir = "dts/upstream/src/arm64/rockchip";
+			filename-pattern = "alt-NAME.bin";
+			fdt-phase = "tpl";
+
+			mkimage {
+				filename = "idbloader.img";
+				args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
+				multiple-data-files;
+
+				u-boot-tpl {
+					symbols-base = <0>;
+				};
+			};
+		};
+
+		vpl {
+			type = "fit";
+			offset = <(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 0x200)>;
+			description = "FIT image for U-Boot TPL";
+			#address-cells = <1>;
+			fit,fdt-list = "of-list";
+			fit,align = <512>;
+			fit,external-offset = <0>;
+			images {
+				image-vpl {
+					description = "U-Boot VPL";
+					type = "firmware";
+					os = "u-boot";
+					arch = ARCH;
+					compression = "lz4";
+					load = <CONFIG_VPL_TEXT_BASE>;
+					entry = <CONFIG_VPL_TEXT_BASE>;
+					section {
+						compress = "lz4";
+						u-boot-vpl-nodtb {
+							symbols-base = <0>;
+						};
+						u-boot-vpl-bss-pad {
+						};
+					};
+				};
+				@fdt-SEQ {
+					description = "fdt-NAME";
+					compression = "none";
+					type = "flat_dt";
+					fit,fdt-phase = "vpl";
+				};
+			};
+			configurations {
+				default = "@config-DEFAULT-SEQ";
+				@config-SEQ {
+					description = "NAME.dtb";
+					fdt = "fdt-SEQ";
+					fit,firmware = "image-vpl";
+					fit,loadables;
+					fit,compatible;
+				};
+			};
+		};
+# ifdef CONFIG_BOOTMETH_VBE_ABREC
+		vbe-a {
+			type = "section";
+			offset = <CONFIG_SPL_PAD_TO>;
+			spl-a {
+				insert-template = <&spl_template>;
+				size = <0x100000>;
+			};
+
+			u-boot-a {
+				insert-template = <&common_part>;
+			};
+		};
+		vbe-b {
+			type = "section";
+			offset = <0x1000000>;
+			spl-b {
+				insert-template = <&spl_template>;
+				size = <0x100000>;
+			};
+
+			u-boot-b {
+				insert-template = <&common_part>;
+			};
+		};
+		vbe-recovery {
+			type = "section";
+			offset = <0x1800000>;
+			spl-recovery {
+				insert-template = <&spl_template>;
+				size = <0x100000>;
+			};
+
+			u-boot-recovery {
+				insert-template = <&common_part>;
+			};
+		};
+# else /* CONFIG_BOOTMETH_VBE_SIMPLE */
+		vbe {
+			type = "fit";
+			offset = <CONFIG_SPL_PAD_TO>;
+			insert-template = <&common_part>;
+		};
+# endif /* VBE method */
+	};
+};

arch/arm/include/asm/spl.h

@@ -30,6 +30,7 @@ enum {
 	BOOT_DEVICE_XIP,
 	BOOT_DEVICE_BOOTROM,
 	BOOT_DEVICE_SMH,
+	BOOT_DEVICE_VBE,
 	BOOT_DEVICE_NONE
 };
 #endif

arch/arm/lib/crt0.S

@@ -100,10 +100,8 @@ ENTRY(_main)
  * Set up initial C runtime environment and call board_init_f(0).
  */
 
-#if defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_NEEDS_SEPARATE_STACK)
-	ldr	r0, =(CONFIG_TPL_STACK)
-#elif defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK)
-	ldr	r0, =(CONFIG_SPL_STACK)
+#if CONFIG_IS_ENABLED(HAVE_INIT_STACK)
+	ldr	r0, =CONFIG_VAL(STACK)
 #else
 	ldr	r0, =(SYS_INIT_SP_ADDR)
 #endif

arch/arm/lib/crt0_64.S

@@ -69,10 +69,8 @@ ENTRY(_main)
 /*
  * Set up initial C runtime environment and call board_init_f(0).
  */
-#if defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_NEEDS_SEPARATE_STACK)
-	ldr	x0, =(CONFIG_TPL_STACK)
-#elif defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK)
-	ldr	x0, =(CONFIG_SPL_STACK)
+#if CONFIG_IS_ENABLED(HAVE_INIT_STACK)
+	ldr	x0, =CONFIG_VAL(STACK)
 #elif defined(CONFIG_INIT_SP_RELATIVE)
 #if CONFIG_POSITION_INDEPENDENT
 	adrp	x0, __bss_start     /* x0 <- Runtime &__bss_start */

arch/arm/mach-rockchip/Kconfig

@@ -9,7 +9,7 @@ config ROCKCHIP_PX30
 	select SPL
 	select TPL
 	select TPL_TINY_FRAMEWORK if TPL
-	select TPL_NEEDS_SEPARATE_STACK if TPL
+	select TPL_HAVE_INIT_STACK if TPL
 	imply SPL_SEPARATE_BSS
 	select SPL_SERIAL
 	select TPL_SERIAL
@@ -106,7 +106,7 @@ config ROCKCHIP_RK322X
 	select TPL
 	select TPL_DM
 	select TPL_OF_LIBFDT
-	select TPL_NEEDS_SEPARATE_STACK if TPL
+	select TPL_HAVE_INIT_STACK if TPL
 	select SPL_DRIVERS_MISC
 	imply ROCKCHIP_COMMON_BOARD
 	imply SPL_SERIAL
@@ -139,7 +139,7 @@ config ROCKCHIP_RK3288
 	imply TPL_DRIVERS_MISC
 	imply TPL_LIBCOMMON_SUPPORT
 	imply TPL_LIBGENERIC_SUPPORT
-	imply TPL_NEEDS_SEPARATE_STACK
+	imply TPL_HAVE_INIT_STACK
 	imply TPL_OF_CONTROL
 	imply TPL_OF_PLATDATA
 	imply TPL_RAM
@@ -197,7 +197,7 @@ config ROCKCHIP_RK3328
 	select SPL
 	select SUPPORT_TPL
 	select TPL
-	select TPL_NEEDS_SEPARATE_STACK if TPL
+	select TPL_HAVE_INIT_STACK if TPL
 	imply ARMV8_CRYPTO
 	imply ARMV8_SET_SMPEN
 	imply MISC
@@ -225,7 +225,7 @@ config ROCKCHIP_RK3368
 	select ARM64
 	select SUPPORT_SPL
 	select SUPPORT_TPL
-	select TPL_NEEDS_SEPARATE_STACK if TPL
+	select TPL_HAVE_INIT_STACK if TPL
 	imply ROCKCHIP_COMMON_BOARD
 	imply SPL_ROCKCHIP_COMMON_BOARD
 	imply SPL_SEPARATE_BSS
@@ -252,13 +252,15 @@ config ROCKCHIP_RK3399
 	select SPL_ATF
 	select SPL_BOARD_INIT if SPL
 	select SPL_LOAD_FIT
-	select SPL_CLK if SPL
+	select SPL_CLK if SPL && !VPL
 	select SPL_PINCTRL if SPL
 	select SPL_RAM if SPL
 	select SPL_REGMAP if SPL
 	select SPL_SYSCON if SPL
-	select TPL_NEEDS_SEPARATE_STACK if TPL
-	select SPL_SEPARATE_BSS
+	select TPL_HAVE_INIT_STACK if TPL
+	select VPL_HAVE_INIT_STACK if VPL
+	select SPL_SEPARATE_BSS if !VPL
+	select SPL_RAW_IMAGE_SUPPORT if VPL
 	select CLK
 	select FIT
 	select PINCTRL
@@ -268,6 +270,7 @@ config ROCKCHIP_RK3399
 	select DM_PMIC
 	select DM_REGULATOR_FIXED
 	select BOARD_LATE_INIT
+	select SUPPORT_VPL
 	imply ARMV8_CRYPTO
 	imply ARMV8_SET_SMPEN
 	imply BOOTSTD_FULL
@@ -296,13 +299,14 @@ config ROCKCHIP_RK3399
 	imply TPL_LIBCOMMON_SUPPORT
 	imply TPL_LIBGENERIC_SUPPORT
 	imply TPL_OF_CONTROL
-	imply TPL_RAM
+	imply TPL_RAM if !VPL
 	imply TPL_REGMAP
 	imply TPL_ROCKCHIP_COMMON_BOARD
 	imply TPL_SERIAL
 	imply TPL_SYS_MALLOC_SIMPLE
 	imply TPL_SYSCON
 	imply TPL_TINY_MEMSET
+	imply TPL_DM_MMC if VPL
 	help
 	  The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
 	  and quad-core Cortex-A53.
@@ -392,7 +396,7 @@ config ROCKCHIP_RV1126
 	select SKIP_LOWLEVEL_INIT_ONLY
 	select TPL
 	select SUPPORT_TPL
-	select TPL_NEEDS_SEPARATE_STACK
+	select TPL_HAVE_INIT_STACK
 	select TPL_ROCKCHIP_BACK_TO_BROM
 	select SPL
 	select SUPPORT_SPL
@@ -457,7 +461,7 @@ config SPL_ROCKCHIP_BACK_TO_BROM
 
 config TPL_ROCKCHIP_BACK_TO_BROM
 	bool "TPL returns to bootrom"
-	default y
+	default y if !VPL
 	select ROCKCHIP_BROM_HELPER if !ROCKCHIP_RK3066
 	select TPL_BOOTROM_SUPPORT
 	depends on TPL
@@ -498,6 +502,16 @@ config ROCKCHIP_EXTERNAL_TPL
 	  Enable this option and build with ROCKCHIP_TPL=/path/to/ddr.bin to
 	  include the external TPL in the image built by binman.
 
+config VPL_ROCKCHIP_COMMON_BOARD
+	bool "Rockchip VPL common board file"
+	depends on VPL
+	default y
+	help
+	  Enable the VPL phase for rockchip, which selects which SPL/U-Boot
+	  will be used on each boot. With this flow, used by Verified Boot for
+	  Embedded (VBE), TPL is loaded by the boot ROM. Then TPL loads VPL,
+	  VPL loads SPL and SPL loads U-Boot.
+
 config ROCKCHIP_BOOT_MODE_REG
 	hex "Rockchip boot mode flag register address"
 	help
@@ -589,6 +603,9 @@ config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
 config SPL_MMC
 	default y if !SPL_ROCKCHIP_BACK_TO_BROM
 
+config TPL_MMC
+	default y if !TPL_ROCKCHIP_BACK_TO_BROM
+
 config ROCKCHIP_SPI_IMAGE
 	bool "Build a SPI image for rockchip"
 	help

arch/arm/mach-rockchip/Makefile

@@ -8,11 +8,16 @@
 # inaccessible/protected memory (and the bootrom-helper assumes that
 # the stack-pointer is valid before switching to the U-Boot stack).
 obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
-obj-spl-$(CONFIG_SPL_ROCKCHIP_COMMON_BOARD) += spl.o spl-boot-order.o spl_common.o
+obj-spl-$(CONFIG_SPL_ROCKCHIP_COMMON_BOARD) += spl.o spl_common.o
+ifndef CONFIG_VPL
+obj-spl-$(CONFIG_SPL_ROCKCHIP_COMMON_BOARD) += spl-boot-order.o
+endif
 obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
 obj-tpl-$(CONFIG_TPL_ROCKCHIP_COMMON_BOARD) += tpl.o spl_common.o
 obj-tpl-$(CONFIG_ROCKCHIP_PX30) += px30-board-tpl.o
 
+obj-vpl-$(CONFIG_VPL_ROCKCHIP_COMMON_BOARD) += vpl.o
+
 obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
 
 ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_TPL_BUILD),)
@@ -47,9 +52,11 @@ obj-$(CONFIG_ROCKCHIP_RK3588) += rk3588/
 obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/
 obj-$(CONFIG_ROCKCHIP_RV1126) += rv1126/
 
-# Clear out SPL objects, in case this is a TPL build
+# Clear out SPL objects, in case this is a TPL or VPL build
 obj-spl-$(CONFIG_TPL_BUILD) =
+obj-spl-$(CONFIG_VPL_BUILD) =
 
 # Now add SPL/TPL objects back into the main build
 obj-$(CONFIG_XPL_BUILD) += $(obj-spl-y)
 obj-$(CONFIG_TPL_BUILD) += $(obj-tpl-y)
+obj-$(CONFIG_VPL_BUILD) += $(obj-vpl-y)

arch/arm/mach-rockchip/rk3399/Kconfig

@@ -159,11 +159,20 @@ config TPL_LDSCRIPT
 	default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
 
 config TPL_STACK
-        default 0xff8effff
+        default 0xff8eff00
 
 config TPL_TEXT_BASE
         default 0xff8c2000
 
+config VPL_STACK
+        default 0xff8eff00
+
+config VPL_TEXT_BASE
+        default 0xff8c2000
+
+config VPL_LDSCRIPT
+	default "arch/arm/mach-rockchip/u-boot-vpl-v8.lds"
+
 config SPL_STACK_R_ADDR
 	default 0x04000000 if !SPL_SHARES_INIT_SP_ADDR
 

arch/arm/mach-rockchip/spl.c

@@ -3,6 +3,7 @@
  * (C) Copyright 2019 Rockchip Electronics Co., Ltd
  */
 
+#include <bloblist.h>
 #include <cpu_func.h>
 #include <debug_uart.h>
 #include <dm.h>
@@ -61,6 +62,9 @@ u32 spl_boot_device(void)
 {
 	u32 boot_device = BOOT_DEVICE_MMC1;
 
+	if (IS_ENABLED(CONFIG_VPL))
+		return BOOT_DEVICE_VBE;
+
 #if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
 		defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
 		defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) || \
@@ -130,6 +134,19 @@ void board_init_f(ulong dummy)
 
 void spl_board_prepare_for_boot(void)
 {
+	/*
+	 * On RK3399, TF-A is executed after SPL and before U-Boot. It removes
+	 * our access to the IRAM. So move the bloblist to RAM.
+	 */
+	if (xpl_phase() == PHASE_SPL && IS_ENABLED(CONFIG_VPL)) {
+		ulong addr = CONFIG_IF_ENABLED_INT(BLOBLIST_RELOC,
+						   BLOBLIST_RELOC_ADDR);
+
+		log_debug("Relocating bloblist %p to %lx\n", gd_bloblist(),
+			  addr);
+		bloblist_reloc(map_sysmem(addr, 0), bloblist_get_total_size());
+	}
+
 	if (!IS_ENABLED(CONFIG_ARM64) || CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
 		return;
 

arch/arm/mach-rockchip/tpl.c

@@ -60,10 +60,12 @@ void board_init_f(ulong dummy)
 
 	tpl_board_init();
 
-	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
-	if (ret) {
-		printf("DRAM init failed: %d\n", ret);
-		return;
+	if (CONFIG_IS_ENABLED(RAM)) {
+		ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+		if (ret) {
+			printf("DRAM init failed: %d\n", ret);
+			return;
+		}
 	}
 }
 
@@ -84,5 +86,5 @@ int board_return_to_bootrom(struct spl_image_info *spl_image,
 
 u32 spl_boot_device(void)
 {
-	return BOOT_DEVICE_BOOTROM;
+	return IS_ENABLED(CONFIG_VPL) ? BOOT_DEVICE_VBE : BOOT_DEVICE_BOOTROM;
 }

arch/arm/mach-rockchip/u-boot-tpl-v8.lds

@@ -25,10 +25,21 @@ SECTIONS
 	__image_copy_start = ADDR(.text);
 	.text : {
 		. = ALIGN(8);
+		__image_copy_start = .;
 		CPUDIR/start.o (.text*)
+
+		/* put relocation code all together */
+		//. = . + 0xc0;
+		_rcode_start = .;
+		*(.text.rcode)
+		*(.text.rdata)
+		_rcode_end = .;
+
 		*(.text*)
 	}
 
+	_rcode_size = _rcode_end - _rcode_start;
+
 	.rodata : {
 		. = ALIGN(8);
 		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
@@ -48,6 +59,7 @@ SECTIONS
 	__image_copy_end = .;
 	_end = .;
 	_image_binary_end = .;
+	__image_copy_end = .;
 
 	.bss ALIGN(8) : {
 		__bss_start = .;
@@ -55,6 +67,7 @@ SECTIONS
 		. = ALIGN(8);
 		__bss_end = .;
 	}
+	__bss_size = __bss_end - __bss_start;
 
 	/DISCARD/ : { *(.dynsym) }
 	/DISCARD/ : { *(.dynstr*) }

arch/arm/mach-rockchip/u-boot-vpl-v8.lds

@@ -0,0 +1,107 @@
+// SPDX-License-Identifier:	GPL-2.0+
+/*
+ * (C) Copyright 2019
+ * Rockchip Electronics Co., Ltd
+ * Kever Yang<kever.yang@rock-chips.com>
+ *
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *	Aneesh V <aneesh@ti.com>
+ */
+
+OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
+OUTPUT_ARCH(aarch64)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	.text : {
+		. = ALIGN(8);
+		__image_copy_start = .;
+		CPUDIR/start.o (.text*)
+
+		/* put relocation code all together */
+		//. = . + 0xc0;
+		_rcode_start = .;
+		*(.text.rcode)
+		*(.text.rdata)
+		_rcode_end = .;
+
+		*(.text*)
+	}
+
+	.rodata : {
+		. = ALIGN(8);
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	}
+
+	.data : {
+		. = ALIGN(8);
+		*(.data*)
+	}
+
+	__u_boot_list : {
+		. = ALIGN(8);
+		KEEP(*(SORT(__u_boot_list*)));
+	}
+
+	.image_copy_end : {
+		. = ALIGN(8);
+		*(.__image_copy_end)
+	}
+
+	.end : {
+		. = ALIGN(8);
+		*(.__end)
+	}
+
+	_image_binary_end = .;
+	_end = .;
+	__image_copy_end = .;
+
+	__bss_start = .;
+	.bss_start (NOLOAD) : {
+		. = ALIGN(8);
+		KEEP(*(.__bss_start));
+	}
+
+	.bss (NOLOAD) : {
+		*(.bss*)
+		 . = ALIGN(8);
+	}
+
+	.bss_end (NOLOAD) : {
+		KEEP(*(.__bss_end));
+	}
+	__bss_end = .;
+	__bss_size = __bss_end - __bss_start;
+
+	/DISCARD/ : { *(.dynsym) }
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
+}
+
+#if defined(CONFIG_TPL_MAX_SIZE)
+ASSERT(__image_copy_end - __image_copy_start < (CONFIG_TPL_MAX_SIZE), \
+	"TPL image too big");
+#endif
+
+#if defined(CONFIG_TPL_BSS_MAX_SIZE)
+ASSERT(__bss_end - __bss_start < (CONFIG_TPL_BSS_MAX_SIZE), \
+	"TPL image BSS too big");
+#endif
+
+#if defined(CONFIG_TPL_MAX_FOOTPRINT)
+ASSERT(__bss_end - _start < (CONFIG_TPL_MAX_FOOTPRINT), \
+	"TPL image plus BSS too big");
+#endif

arch/arm/mach-rockchip/vpl.c

@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#include <bootstage.h>
+#include <debug_uart.h>
+#include <dm.h>
+#include <hang.h>
+#include <init.h>
+#include <log.h>
+#include <ram.h>
+#include <spl.h>
+#include <version.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/bootrom.h>
+#include <linux/bitops.h>
+
+#if CONFIG_IS_ENABLED(BANNER_PRINT)
+#include <timestamp.h>
+#endif
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_VPL_SERIAL)
+	/*
+	 * Debug UART can be used from here if required:
+	 *
+	 * debug_uart_init();
+	 * printch('a');
+	 * printhex8(0x1234);
+	 * printascii("string");
+	 */
+	debug_uart_init();
+#ifdef CONFIG_VPL_BANNER_PRINT
+	printascii("\nU-Boot VPL " PLAIN_VERSION " (" U_BOOT_DATE " - "
+		   U_BOOT_TIME ")\n");
+#endif
+#endif
+
+	ret = spl_early_init();
+	if (ret) {
+		debug("spl_early_init() failed: %d\n", ret);
+		hang();
+	}
+}
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_VBE;
+}

arch/riscv/cpu/start.S

@@ -90,8 +90,8 @@ _start:
  * Set stackpointer in internal/ex RAM to call board_init_f
  */
 call_board_init_f:
-#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK)
-	li	t0, CONFIG_SPL_STACK
+#if CONFIG_IS_ENABLED(HAVE_INIT_STACK)
+	li	t0, CONFIG_VAL(STACK)
 #else
 	li	t0, SYS_INIT_SP_ADDR
 #endif

board/rockchip/evb_rk3399/MAINTAINERS

@@ -89,3 +89,9 @@ M:	Jagan Teki <jagan@amarulasolutions.com>
 S:	Maintained
 F:	configs/rock-pi-n10-rk3399pro_defconfig
 F:	arch/arm/dts/rk3399pro-rock-pi-n10*
+
+RK3399-GENERIC-DDR3
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	configs/rk3399-generic-ddr3_defconfig
+F:	arch/arm/dts/rockchip-vpl-u-boot.dtsi

boot/vbe_abrec.c

@@ -8,6 +8,7 @@
 
 #define LOG_CATEGORY LOGC_BOOT
 
+#include <bootmeth.h>
 #include <dm.h>
 #include <memalign.h>
 #include <mmc.h>
@@ -81,3 +82,101 @@ int abrec_read_state(struct udevice *dev, struct abrec_state *state)
 
 	return 0;
 }
+
+static int vbe_abrec_get_state_desc(struct udevice *dev, char *buf,
+				     int maxsize)
+{
+	struct abrec_state state;
+	int ret;
+
+	ret = abrec_read_state(dev, &state);
+	if (ret)
+		return log_msg_ret("read", ret);
+
+	if (maxsize < 30)
+		return -ENOSPC;
+	snprintf(buf, maxsize, "Version: %s\nVernum: %x/%x", state.fw_version,
+		 state.fw_vernum >> FWVER_KEY_SHIFT,
+		 state.fw_vernum & FWVER_FW_MASK);
+
+	return 0;
+}
+
+static int vbe_abrec_read_bootflow(struct udevice *dev, struct bootflow *bflow)
+{
+	int ret;
+
+	if (CONFIG_IS_ENABLED(BOOTMETH_VBE_ABREC_FW)) {
+		if (vbe_phase() == VBE_PHASE_FIRMWARE) {
+			ret = abrec_read_bootflow_fw(dev, bflow);
+			if (ret)
+				return log_msg_ret("fw", ret);
+			return 0;
+		}
+	}
+
+	return -EINVAL;
+}
+
+static int vbe_abrec_read_file(struct udevice *dev, struct bootflow *bflow,
+				const char *file_path, ulong addr,
+				enum bootflow_img_t type, ulong *sizep)
+{
+	int ret;
+
+	if (vbe_phase() == VBE_PHASE_OS) {
+		ret = bootmeth_common_read_file(dev, bflow, file_path, addr,
+						type, sizep);
+		if (ret)
+			return log_msg_ret("os", ret);
+	}
+
+	/* To be implemented */
+	return -EINVAL;
+}
+
+static struct bootmeth_ops bootmeth_vbe_abrec_ops = {
+	.get_state_desc	= vbe_abrec_get_state_desc,
+	.read_bootflow	= vbe_abrec_read_bootflow,
+	.read_file	= vbe_abrec_read_file,
+};
+
+static int bootmeth_vbe_abrec_probe(struct udevice *dev)
+{
+	struct abrec_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = abrec_read_priv(dev_ofnode(dev), priv);
+	if (ret)
+		return log_msg_ret("abp", ret);
+
+	return 0;
+}
+
+static int bootmeth_vbe_abrec_bind(struct udevice *dev)
+{
+	struct bootmeth_uc_plat *plat = dev_get_uclass_plat(dev);
+
+	plat->desc = "VBE A/B/recovery";
+	plat->flags = BOOTMETHF_GLOBAL;
+
+	return 0;
+}
+
+#if CONFIG_IS_ENABLED(OF_REAL)
+static const struct udevice_id generic_simple_vbe_abrec_ids[] = {
+	{ .compatible = "fwupd,vbe-abrec" },
+	{ }
+};
+#endif
+
+U_BOOT_DRIVER(vbe_abrec) = {
+	.name	= "vbe_abrec",
+	.id	= UCLASS_BOOTMETH,
+	.of_match = of_match_ptr(generic_simple_vbe_abrec_ids),
+	.ops	= &bootmeth_vbe_abrec_ops,
+	.bind	= bootmeth_vbe_abrec_bind,
+	.probe	= bootmeth_vbe_abrec_probe,
+	.flags	= DM_FLAG_PRE_RELOC,
+	.priv_auto	= sizeof(struct abrec_priv),
+};

cmd/vbe.c

@@ -92,9 +92,13 @@ static int do_vbe_state(struct cmd_tbl *cmdtp, int flag, int argc,
 
 	printf("Phases:");
 	for (i = PHASE_NONE; i < PHASE_COUNT; i++) {
-		if (handoff->phases & (1 << i))
-			printf(" %s", xpl_name(i));
+		if (handoff->phases & (1 << i)) {
+			int margin = handoff->reloc_margin[i];
 
+			printf(" %s", xpl_name(i));
+			if (margin)
+				printf(" (margin %x) ", margin);
+		}
 	}
 	if (!handoff->phases)
 		printf(" (none)");

common/Kconfig

@@ -1125,6 +1125,26 @@ config SPL_BLOBLIST_ALLOC
 
 endchoice
 
+config SPL_BLOBLIST_RELOC
+	bool "Relocate the bloblist before existing SPL"
+	depends on BLOBLIST_FIXED
+	help
+	  Some platforms locate the bloblist in SRAM in SPL. In some cases,
+	  the TF-A BL31 blob removes access to SRAM, e.g. with Rockchip RK3399.
+
+	  Enable this option to make U-Boot copy the bloblist from SRAM to SDRAM
+	  before leaving SPL.
+
+config SPL_BLOBLIST_RELOC_ADDR
+	hex "Relocate the bloblist before existing SPL"
+	depends on SPL_BLOBLIST_RELOC
+	default BLOBLIST_ADDR
+	help
+	  Sets the address to which the bloblist is relocated at the end of SPL.
+	  U-Boot proper uses this address when it starts up. Note that U-Boot
+	  always relocates the bloblist again as part of its own relocation
+	  process.
+
 endif # SPL_BLOBLIST
 
 if TPL_BLOBLIST

common/bloblist.c

@@ -487,57 +487,50 @@ int bloblist_reloc(void *to, uint to_size)
 	return 0;
 }
 
-/*
- * Weak default function for getting bloblist from boot args.
- */
-int __weak xferlist_from_boot_arg(ulong __always_unused addr,
-				  ulong __always_unused size)
-{
-	return -ENOENT;
-}
-
 int bloblist_init(void)
 {
 	bool fixed = IS_ENABLED(CONFIG_BLOBLIST_FIXED);
 	int ret = -ENOENT;
-	ulong addr = 0, size;
-	/*
-	 * If U-Boot is not in the first phase, an existing bloblist must be
-	 * at a fixed address.
-	 */
-	bool from_addr = fixed && !xpl_is_first_phase();
-	/*
-	 * If U-Boot is in the first phase that an arch custom routine should
-	 * install the bloblist passed from previous loader to this fixed
+	ulong addr, size;
+	bool expected;
+
+	/**
+	 * We don't expect to find an existing bloblist in the first phase of
+	 * U-Boot that runs. Also we have no way to receive the address of an
+	 * allocated bloblist from a previous stage, so it must be at a fixed
 	 * address.
 	 */
-	bool from_boot_arg = fixed && xpl_is_first_phase();
-
+	expected = fixed && !xpl_is_first_phase();
 	if (xpl_prev_phase() == PHASE_TPL && !IS_ENABLED(CONFIG_TPL_BLOBLIST))
-		from_addr = false;
-	if (fixed)
+		expected = false;
+	if (fixed) {
 		addr = IF_ENABLED_INT(CONFIG_BLOBLIST_FIXED,
 				      CONFIG_BLOBLIST_ADDR);
+
+		if (xpl_phase() == PHASE_BOARD_F &&
+		    IS_ENABLED(CONFIG_SPL_BLOBLIST_RELOC)) {
+			ulong addr = IF_ENABLED_INT(CONFIG_SPL_BLOBLIST_RELOC,
+					    CONFIG_SPL_BLOBLIST_RELOC_ADDR);
+
+			log_debug("Using bloblist at %lx\n", addr);
+			bloblist_reloc(map_sysmem(addr, 0),
+				       bloblist_get_total_size());
+		}
+		log_debug("bloblist addr=%lx\n", addr);
+	}
+
 	size = CONFIG_BLOBLIST_SIZE;
-
-	if (from_boot_arg)
-		ret = xferlist_from_boot_arg(addr, size);
-	else if (from_addr)
+	if (expected) {
 		ret = bloblist_check(addr, size);
-
-	if (ret)
-		log_warning("Bloblist at %lx not found (err=%d)\n",
-			    addr, ret);
-	else
-		/* Get the real size */
-		size = gd->bloblist->total_size;
-
+		if (ret) {
+			log_warning("Expected bloblist at %lx not found (err=%d)\n",
+				    addr, ret);
+		} else {
+			/* Get the real size, if it is not what we expected */
+			size = gd->bloblist->total_size;
+		}
+	}
 	if (ret) {
-		/*
-		 * If we don't have a bloblist from a fixed address, or the one
-		 * in the fixed address is not valid. we must allocate the
-		 * memory for it now.
-		 */
 		if (CONFIG_IS_ENABLED(BLOBLIST_ALLOC)) {
 			void *ptr = memalign(BLOBLIST_ALIGN, size);
 
@@ -545,8 +538,7 @@ int bloblist_init(void)
 				return log_msg_ret("alloc", -ENOMEM);
 			addr = map_to_sysmem(ptr);
 		} else if (!fixed) {
-			return log_msg_ret("BLOBLIST_FIXED is not enabled",
-					   ret);
+			return log_msg_ret("!fixed", ret);
 		}
 		log_debug("Creating new bloblist size %lx at %lx\n", size,
 			  addr);
@@ -559,11 +551,6 @@ int bloblist_init(void)
 		return log_msg_ret("ini", ret);
 	gd->flags |= GD_FLG_BLOBLIST_READY;
 
-#ifdef DEBUG
-	bloblist_show_stats();
-	bloblist_show_list();
-#endif
-
 	return 0;
 }
 

common/spl/Kconfig

@@ -387,11 +387,29 @@ config SPL_SHARES_INIT_SP_ADDR
 	  both SPL and U-Boot itself.  If you need to specify a different address
 	  however, say N here and then set a different value in CONFIG_SPL_STACK.
 
-config SPL_STACK
-	hex "Initial stack pointer location"
+config SPL_HAVE_INIT_STACK
+	bool "SPL requires a initial, fixed, stack-pointer location"
 	depends on (ARM || ARCH_JZ47XX || MICROBLAZE || RISCV) && \
 		SPL_FRAMEWORK || ROCKCHIP_RK3036
 	depends on !SPL_SHARES_INIT_SP_ADDR
+	default y if ARCH_MX7
+	default y if ARCH_MX6 && MX6_OCRAM_256KB
+	default y if ARCH_MX6 && !MX6_OCRAM_256KB
+	default y if MACH_SUN50I_H6 || MACH_SUN50I_H616 || MACH_SUN8I_R528
+	default y if MACH_SUN50I || MACH_SUN50I_H5
+	default y if MACH_SUN9I
+	default y if ARCH_SUNXI
+	default y if ARCH_SC5XX && (SC59X_64 || SC59X)
+	default y if ARCH_SC5XX && SC58X
+	default y if ARCH_SC5XX && SC57X
+	help
+	  Enable if the SPL phase should not use inherit its initial
+	  stack-pointer from the settings for U-Boot proper, but should set
+	  its own value.
+
+config SPL_STACK
+	hex "Address of the initial stack-pointer for the SPL phase"
+	depends on SPL_HAVE_INIT_STACK
 	default 0x946bb8 if ARCH_MX7
 	default 0x93ffb8 if ARCH_MX6 && MX6_OCRAM_256KB
 	default 0x91ffb8 if ARCH_MX6 && !MX6_OCRAM_256KB
@@ -401,9 +419,9 @@ config SPL_STACK
 	default 0x54000 if MACH_SUN50I || MACH_SUN50I_H5
 	default 0x18000 if MACH_SUN9I
 	default 0x8000 if ARCH_SUNXI
-	default 0x200E4000 if ARCH_SC5XX && (SC59X_64 || SC59X)
-	default 0x200B0000 if ARCH_SC5XX && SC58X
-	default 0x200D0000 if ARCH_SC5XX && SC57X
+	default 0x200e4000 if ARCH_SC5XX && (SC59X_64 || SC59X)
+	default 0x200b0000 if ARCH_SC5XX && SC58X
+	default 0x200d0000 if ARCH_SC5XX && SC57X
 	help
 	  Address of the start of the stack SPL will use before SDRAM is
 	  initialized.
@@ -554,6 +572,7 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
 	default 0x200 if ARCH_SOCFPGA || ARCH_AT91
 	default 0x300 if ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \
 		         OMAP54XX || AM33XX || AM43XX || ARCH_K3
+	default 0x800 if ARCH_ROCKCHIP && VPL
 	default 0x4000 if ARCH_ROCKCHIP
 	default 0x822 if TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED
 	help

common/spl/Kconfig.tpl

@@ -106,12 +106,6 @@ config TPL_LDSCRIPT
 	  May be left empty to trigger the Makefile infrastructure to
 	  fall back to the linker-script used for the SPL stage.
 
-config TPL_NEEDS_SEPARATE_STACK
-	bool "TPL needs a separate initial stack-pointer"
-	help
-	  Enable, if the TPL stage should not inherit its initial
-	  stack-pointer from the settings for the SPL stage.
-
 config TPL_POWER
 	bool "Support power drivers"
 	help
@@ -140,11 +134,18 @@ config TPL_MAX_SIZE
 	help
 	  The maximum size (in bytes) of the TPL stage.
 
-config TPL_STACK
-	hex "Address of the initial stack-pointer for the TPL stage"
-	depends on TPL_NEEDS_SEPARATE_STACK
+config TPL_HAVE_INIT_STACK
+	bool "TPL requires a initial, fixed, stack-pointer location"
 	help
-	  The address of the initial stack-pointer for the TPL stage.
+	  Enable if the TPL phase should not use inherit its initial
+	  stack-pointer from the settings for U-Boot proper, but should set
+	  its own value.
+
+config TPL_STACK
+	hex "Address of the initial stack-pointer for the TPL phase"
+	depends on TPL_HAVE_INIT_STACK
+	help
+	  The address of the initial stack-pointer for the TPL phase
 	  Usually this will be the (aligned) top-of-stack.
 
 config TPL_READ_ONLY

common/spl/Kconfig.vpl

@@ -266,6 +266,20 @@ config VPL_MAX_SIZE
 	  The maximum size (in bytes) of the TPL stage. This size is determined
 	  by the amount of internal SRAM memory.
 
+config VPL_HAVE_INIT_STACK
+	bool "VPL requires a initial, fixed, stack-pointer location"
+	help
+	  Enable if the VPL phase should not use inherit its initial
+	  stack-pointer from the settings for U-Boot proper, but should set
+	  its own value.
+
+config VPL_STACK
+	hex "Address of the initial stack-pointer for the VPL stage"
+	depends on VPL_HAVE_INIT_STACK
+	help
+	  The address of the initial stack-pointer for the VPL stage.
+	  Usually this will be the (aligned) top-of-stack.
+
 config VPL_BINMAN_SYMBOLS
 	bool "Declare binman symbols in VPL"
 	depends on VPL_FRAMEWORK && BINMAN

common/spl/spl.c

@@ -200,6 +200,8 @@ ulong spl_get_image_size(void)
 #ifdef CONFIG_VPL
 	if (xpl_next_phase() == PHASE_VPL)
 		return binman_sym(ulong, u_boot_vpl_any, size);
+
+	return 0;	/* VBE handles this */
 #endif
 	return xpl_next_phase() == PHASE_SPL ?
 		binman_sym(ulong, u_boot_spl_any, size) :

common/spl/spl_reloc.c

@@ -4,11 +4,13 @@
  * Written by Simon Glass <sjg@chromium.org>
  */
 
+#include <bloblist.h>
 #include <gzip.h>
 #include <image.h>
 #include <log.h>
 #include <mapmem.h>
 #include <spl.h>
+#include <vbe.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
 #include <asm/sections.h>
@@ -58,8 +60,18 @@ static int setup_layout(struct spl_image_info *image, ulong *addrp)
 	buf_size = rcode_base - base;
 	uint need_size = image->size + image->fdt_size;
 	margin = buf_size - need_size;
+
+	if (CONFIG_IS_ENABLED(BLOBLIST)) {
+		struct vbe_handoff *handoff;
+
+		handoff = bloblist_find(BLOBLISTT_VBE,
+					sizeof(struct vbe_handoff));
+		if (handoff)
+			handoff->reloc_margin[xpl_phase()] = margin;
+	}
+
 	log_debug("spl_reloc %s->%s: margin%s%lx limit %lx fdt_size %lx base %lx avail %x image %x fdt %lx need %x\n",
-		  spl_phase_name(spl_phase()), spl_phase_name(spl_phase() + 1),
+		  xpl_name(xpl_phase()), xpl_name(xpl_phase() + 1),
 		  margin >= 0 ? " " : " -", abs(margin), limit, fdt_size, base,
 		  buf_size, image->size, image->fdt_size, need_size);
 	if (margin < 0) {

configs/alt_defconfig

@@ -14,6 +14,7 @@ CONFIG_ARCH_RENESAS_BOARD_STRING="Alt"
 CONFIG_R8A7794=y
 CONFIG_TARGET_ALT=y
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0xe6340000
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL=y

configs/anbernic-rgxx3-rk3566_defconfig

@@ -28,7 +28,7 @@ CONFIG_BOARD_TYPES=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_RNG_SEED=y
 CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
 CONFIG_SPL_BOARD_INIT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_POWER=y

configs/apalis-tk1_defconfig

@@ -9,6 +9,7 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFDE00
 CONFIG_DEFAULT_DEVICE_TREE="tegra124-apalis"
 CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x800ffffc
 CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SYS_LOAD_ADDR=0x81000000

configs/apalis_t30_defconfig

@@ -9,6 +9,7 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFDE00
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-apalis"
 CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x800ffffc
 CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SYS_LOAD_ADDR=0x81000000

configs/axm_defconfig

@@ -19,6 +19,7 @@ CONFIG_SPL_LDSCRIPT="arch/arm/cpu/u-boot-spl.lds"
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus"
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x304000
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

configs/beaver_defconfig

@@ -9,6 +9,7 @@ CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFE000
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-beaver"
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x800ffffc
 CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SYS_LOAD_ADDR=0x81000000

configs/bitmain_antminer_s9_defconfig

@@ -11,6 +11,7 @@ CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="bitmain-antminer-s9"
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_SYS_BOOTCOUNT_ADDR=0xEFFFFF0
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0xfffffe00
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x100000

configs/bpi-r2-pro-rk3568_defconfig

@@ -19,7 +19,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-bpi-r2-pro.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_ATF=y
 CONFIG_SYS_PROMPT="BPI-R2PRO> "

configs/capricorn_cxg3_defconfig

@@ -18,6 +18,7 @@ CONFIG_TARGET_CAPRICORN=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x13e000
 CONFIG_SPL_TEXT_BASE=0x100000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

configs/cardhu_defconfig

@@ -9,6 +9,7 @@ CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFE000
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-cardhu"
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x800ffffc
 CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SYS_LOAD_ADDR=0x81000000

configs/cei-tk1-som_defconfig

@@ -9,6 +9,7 @@ CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFE000
 CONFIG_DEFAULT_DEVICE_TREE="tegra124-cei-tk1-som"
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x800ffffc
 CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SYS_LOAD_ADDR=0x81000000

configs/cgtqmx8_defconfig

@@ -16,6 +16,7 @@ CONFIG_TARGET_CONGA_QMX8=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x13e000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x128000

configs/chromebit_mickey_defconfig

@@ -15,6 +15,7 @@ CONFIG_ROCKCHIP_RK3288=y
 # CONFIG_SPL_MMC is not set
 CONFIG_TARGET_CHROMEBIT_MICKEY=y
 CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0xff718000
 CONFIG_SPL_TEXT_BASE=0xff704000
 CONFIG_SPL_STACK_R=y
@@ -35,7 +36,7 @@ CONFIG_LOG=y
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
 CONFIG_SPL_NO_BSS_LIMIT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set

configs/chromebook_bob_defconfig

@@ -16,6 +16,7 @@ CONFIG_ROCKCHIP_RK3399=y
 CONFIG_ROCKCHIP_BOOT_MODE_REG=0
 CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
 # CONFIG_SPL_MMC is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0xff8effff
 CONFIG_SPL_TEXT_BASE=0xff8c2000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
@@ -39,7 +40,7 @@ CONFIG_BLOBLIST=y
 CONFIG_BLOBLIST_ADDR=0x100000
 CONFIG_BLOBLIST_SIZE=0x1000
 CONFIG_SPL_MAX_SIZE=0x1e000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
 CONFIG_HANDOFF=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set

configs/chromebook_jerry_defconfig

@@ -14,6 +14,7 @@ CONFIG_SYS_MONITOR_LEN=614400
 CONFIG_ROCKCHIP_RK3288=y
 # CONFIG_SPL_MMC is not set
 CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0xff718000
 CONFIG_SPL_TEXT_BASE=0xff704000
 CONFIG_SPL_STACK_R=y
@@ -34,7 +35,7 @@ CONFIG_LOG=y
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
 CONFIG_SPL_NO_BSS_LIMIT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set

configs/chromebook_kevin_defconfig

@@ -17,6 +17,7 @@ CONFIG_ROCKCHIP_BOOT_MODE_REG=0
 CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
 # CONFIG_SPL_MMC is not set
 CONFIG_TARGET_CHROMEBOOK_KEVIN=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0xff8effff
 CONFIG_SPL_TEXT_BASE=0xff8c2000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
@@ -40,7 +41,7 @@ CONFIG_BLOBLIST=y
 CONFIG_BLOBLIST_ADDR=0x100000
 CONFIG_BLOBLIST_SIZE=0x1000
 CONFIG_SPL_MAX_SIZE=0x1e000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
 CONFIG_HANDOFF=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set

configs/chromebook_minnie_defconfig

@@ -15,6 +15,7 @@ CONFIG_ROCKCHIP_RK3288=y
 # CONFIG_SPL_MMC is not set
 CONFIG_TARGET_CHROMEBOOK_MINNIE=y
 CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0xff718000
 CONFIG_SPL_TEXT_BASE=0xff704000
 CONFIG_SPL_STACK_R=y
@@ -35,7 +36,7 @@ CONFIG_LOG=y
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
 CONFIG_SPL_NO_BSS_LIMIT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set

configs/chromebook_speedy_defconfig

@@ -15,6 +15,7 @@ CONFIG_ROCKCHIP_RK3288=y
 # CONFIG_SPL_MMC is not set
 CONFIG_TARGET_CHROMEBOOK_SPEEDY=y
 CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0xff718000
 CONFIG_SPL_TEXT_BASE=0xff704000
 CONFIG_SPL_STACK_R=y
@@ -35,7 +36,7 @@ CONFIG_LOG=y
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
 CONFIG_SPL_NO_BSS_LIMIT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set

configs/ci20_mmc_defconfig

@@ -10,6 +10,7 @@ CONFIG_ENV_OFFSET=0x83800
 CONFIG_DEFAULT_DEVICE_TREE="ci20"
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0xf4008000
 CONFIG_SPL_TEXT_BASE=0xf4000a00
 CONFIG_SPL_BSS_START_ADDR=0xf4004000

configs/clearfog_defconfig

@@ -12,6 +12,7 @@ CONFIG_TARGET_CLEARFOG=y
 CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC=y
 CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog"
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x4002c000
 CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

configs/clearfog_sata_defconfig

@@ -12,6 +12,7 @@ CONFIG_TARGET_CLEARFOG=y
 CONFIG_MVEBU_SPL_BOOT_DEVICE_SATA=y
 CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog"
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x4002c000
 CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

configs/clearfog_spi_defconfig

@@ -12,6 +12,7 @@ CONFIG_TARGET_CLEARFOG=y
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog"
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x4002c000
 CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

configs/cm3588-nas-rk3588_defconfig

@@ -21,7 +21,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-friendlyelec-cm3588-nas.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_ATF=y
 CONFIG_CMD_GPIO=y

configs/colibri_t20_defconfig

@@ -9,6 +9,7 @@ CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x200000
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-colibri"
 CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0xffffc
 CONFIG_SPL_TEXT_BASE=0x00108000
 CONFIG_SYS_LOAD_ADDR=0x1000000

configs/colibri_t30_defconfig

@@ -9,6 +9,7 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFDE00
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-colibri"
 CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x800ffffc
 CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SYS_LOAD_ADDR=0x81000000

configs/controlcenterdc_defconfig

@@ -15,6 +15,7 @@ CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DEFAULT_DEVICE_TREE="armada-38x-controlcenterdc"
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x40031000
 CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

configs/coolpi-4b-rk3588s_defconfig

@@ -27,7 +27,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-coolpi-4b.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000

configs/coolpi-cm5-evb-rk3588_defconfig

@@ -27,7 +27,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-coolpi-cm5-evb.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000

configs/coolpi-cm5-genbook-rk3588_defconfig

@@ -28,7 +28,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-coolpi-cm5-genbook.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000

configs/corvus_defconfig

@@ -19,6 +19,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x70007f00
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="at91sam9g45-corvus"
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x4000
 CONFIG_SPL_TEXT_BASE=0x300000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

configs/da850evm_defconfig

@@ -20,6 +20,7 @@ CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ti/davinci/da850-evm"
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x8001ff00
 CONFIG_SPL_TEXT_BASE=0x80000000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

configs/da850evm_nand_defconfig

@@ -17,6 +17,7 @@ CONFIG_ENV_OFFSET=0x0
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ti/davinci/da850-evm"
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x8001ff00
 CONFIG_SPL_TEXT_BASE=0x80000000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

configs/dalmore_defconfig

@@ -8,6 +8,7 @@ CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFE000
 CONFIG_DEFAULT_DEVICE_TREE="tegra114-dalmore"
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x800ffffc
 CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SYS_LOAD_ADDR=0x81000000

configs/db-88f6720_defconfig

@@ -13,6 +13,7 @@ CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="armada-375-db"
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x4002c000
 CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

configs/db-88f6820-amc_defconfig

@@ -13,6 +13,7 @@ CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DEFAULT_DEVICE_TREE="armada-385-db-88f6820-amc"
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x4002c000
 CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

configs/db-88f6820-amc_nand_defconfig

@@ -15,6 +15,7 @@ CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DEFAULT_DEVICE_TREE="armada-385-db-88f6820-amc"
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x4002c000
 CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

configs/db-88f6820-gp_defconfig

@@ -13,6 +13,7 @@ CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DEFAULT_DEVICE_TREE="armada-388-gp"
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x4002c000
 CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

configs/db-mv784mp-gp_defconfig

@@ -13,6 +13,7 @@ CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="armada-xp-gp"
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x4002c000
 CONFIG_SPL_TEXT_BASE=0x40004030
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

configs/ds116_defconfig

@@ -18,6 +18,7 @@ CONFIG_ENV_OFFSET=0x7E0000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="marvell/armada-385-synology-ds116"
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x4002c000
 CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

configs/ds414_defconfig

@@ -18,6 +18,7 @@ CONFIG_ENV_OFFSET=0x7E0000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="armada-xp-synology-ds414"
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x4002c000
 CONFIG_SPL_TEXT_BASE=0x40004030
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

configs/eaidk-610-rk3399_defconfig

@@ -15,7 +15,7 @@ CONFIG_DEBUG_UART=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-eaidk-610.dtb"
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_TPL=y

configs/endeavoru_defconfig

@@ -9,6 +9,7 @@ CONFIG_ENV_SOURCE_FILE="endeavoru"
 CONFIG_ENV_SIZE=0x3000
 CONFIG_ENV_OFFSET=0xFFFFD000
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-htc-endeavoru"
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x800ffffc
 CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SYS_LOAD_ADDR=0x82000000

configs/evb-px30_defconfig

@@ -25,7 +25,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/px30-evb.dtb"
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x20000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
 CONFIG_SPL_BOOTROM_SUPPORT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_ATF=y

configs/evb-px5_defconfig

@@ -16,6 +16,7 @@ CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_TARGET_EVB_PX5=y
 CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x188000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x400000
@@ -40,7 +41,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-px5-evb.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
 CONFIG_SPL_BOOTROM_SUPPORT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set

configs/evb-rk3036_defconfig

@@ -14,6 +14,7 @@ CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk"
 CONFIG_ROCKCHIP_RK3036=y
 CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x10081fff
 CONFIG_SPL_TEXT_BASE=0x10081000
 CONFIG_SPL_STACK_R=y
@@ -27,7 +28,7 @@ CONFIG_DEFAULT_FDT_FILE="rk3036-evb.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 # CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
 CONFIG_SPL_NO_BSS_LIMIT=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y

configs/evb-rk3229_defconfig

@@ -28,7 +28,7 @@ CONFIG_DEFAULT_FDT_FILE="rk3229-evb.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x100000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
 CONFIG_SPL_NO_BSS_LIMIT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_CMD_GPT=y

configs/evb-rk3288_defconfig

@@ -15,6 +15,7 @@ CONFIG_SYS_MONITOR_LEN=614400
 CONFIG_ROCKCHIP_RK3288=y
 CONFIG_TARGET_EVB_RK3288=y
 CONFIG_SPL_STACK_R_ADDR=0x04000000
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0xff718000
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
@@ -32,7 +33,7 @@ CONFIG_USE_PREBOOT=y
 CONFIG_DEFAULT_FDT_FILE="rk3288-evb-rk808.dtb"
 CONFIG_SILENT_CONSOLE=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
 CONFIG_SPL_NO_BSS_LIMIT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set

configs/evb-rk3308_defconfig

@@ -17,7 +17,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-evb.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y

configs/evb-rk3328_defconfig

@@ -22,7 +22,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-evb.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_ATF=y
 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y

configs/evb-rk3399_defconfig

@@ -16,7 +16,7 @@ CONFIG_DEBUG_UART=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb"
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_TPL=y

configs/evb-rk3568_defconfig

@@ -18,7 +18,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb1-v10.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_ATF=y
 CONFIG_CMD_GPIO=y

configs/evb-rk3588_defconfig

@@ -19,7 +19,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-evb1-v10.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_ATF=y
 CONFIG_CMD_GPIO=y

configs/ficus-rk3399_defconfig

@@ -17,7 +17,7 @@ CONFIG_AHCI=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-ficus.dtb"
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_TPL=y

configs/firefly-px30_defconfig

@@ -26,7 +26,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/px30-firefly.dtb"
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x20000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
 CONFIG_SPL_BOOTROM_SUPPORT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_ATF=y

configs/firefly-rk3288_defconfig

@@ -25,7 +25,7 @@ CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-firefly.dtb"
 CONFIG_MISC_INIT_R=y
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y

configs/firefly-rk3399_defconfig

@@ -17,7 +17,7 @@ CONFIG_DEBUG_UART=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb"
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_TPL=y

configs/gardena-smart-gateway-at91sam_defconfig

@@ -17,6 +17,7 @@ CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91sam9g25-gardena-smart-gateway"
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x308000
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000
 CONFIG_SPL_TEXT_BASE=0x300000

configs/generic-rk3568_defconfig

@@ -23,7 +23,7 @@ CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-generic.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000

configs/generic-rk3588_defconfig

@@ -19,7 +19,7 @@ CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-generic.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_ATF=y
 CONFIG_CMD_GPIO=y

configs/gose_defconfig

@@ -14,6 +14,7 @@ CONFIG_ARCH_RENESAS_BOARD_STRING="Gose"
 CONFIG_R8A7793=y
 CONFIG_TARGET_GOSE=y
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0xe6340000
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL=y

configs/grouper_defconfig

@@ -9,6 +9,7 @@ CONFIG_ENV_SOURCE_FILE="grouper"
 CONFIG_ENV_SIZE=0x3000
 CONFIG_ENV_OFFSET=0xFFFFD000
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-nexus7-grouper-E1565"
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x800ffffc
 CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SYS_LOAD_ADDR=0x82000000

configs/harmony_defconfig

@@ -6,6 +6,7 @@ CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x1FFE0000
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-harmony"
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0xffffc
 CONFIG_SPL_TEXT_BASE=0x00108000
 CONFIG_SYS_LOAD_ADDR=0x1000000

configs/helios4_defconfig

@@ -12,6 +12,7 @@ CONFIG_TARGET_HELIOS4=y
 CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC=y
 CONFIG_DEFAULT_DEVICE_TREE="armada-388-helios4"
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x4002c000
 CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

configs/ideapad-yoga-11_defconfig

@@ -9,6 +9,7 @@ CONFIG_ENV_SOURCE_FILE="ideapad-yoga-11"
 CONFIG_ENV_SIZE=0x3000
 CONFIG_ENV_OFFSET=0xFFFFD000
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-lenovo-ideapad-yoga-11"
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x800ffffc
 CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SYS_LOAD_ADDR=0x82000000

configs/imx28_xea_defconfig

@@ -18,6 +18,7 @@ CONFIG_SPL_MXS_PMU_DISABLE_BATT_CHARGE=y
 # CONFIG_SPL_MXS_PMU_ENABLE_4P2_LINEAR_REGULATOR is not set
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x20000
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000
 CONFIG_SPL_TEXT_BASE=0x1000

configs/imx8mm-cl-iot-gate-optee_defconfig

@@ -14,6 +14,7 @@ CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x920000
 CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

configs/imx8mm-cl-iot-gate_defconfig

@@ -15,6 +15,7 @@ CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x920000
 CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

configs/imx8mm-icore-mx8mm-ctouch2_defconfig

@@ -14,6 +14,7 @@ CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x920000
 CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

configs/imx8mm-icore-mx8mm-edimm2.2_defconfig

@@ -14,6 +14,7 @@ CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x920000
 CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

configs/imx8mm-mx8menlo_defconfig

@@ -17,6 +17,7 @@ CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
 CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x920000
 CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

configs/imx8mm-phygate-tauri-l_defconfig

@@ -14,6 +14,7 @@ CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x920000
 CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

configs/imx8mm_beacon_defconfig

@@ -16,6 +16,7 @@ CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x920000
 CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y